C51 port structure and how it works

The structure and working principle of P0 Port P0 a structure diagram in Port 8-bit see:

By visible, the P0 port consists of a latch, an input buffer, a toggle switch, a and non-gate, A and a gate and a field-effect tube drive circuit. Look at the right side of the picture, labeled p0.x pin icon, that is, the p0.x pin can be P0.0 to P0.7 any one, that is, in the P0 Port has 8 with the same circuit composition.

Now, let's introduce each of the unit parts that make up the P0 port:

First look at the input buffer : In the P0 mouth, there are two three-state buffers, learning the digital circuit, we have known that the three-state gate has three states, that is, its output can be high-level, low-level, while there is a higher-impedance state (or called a prohibited state), you see, The above one is a read latch buffer, that is, to read the D latch output q data, it must be read latch of the buffer of the tri-State control End (the label "read latch" end) valid. The following is a read pin buffer, to read the data on the p0.x pin, but also to the "read pin" of the three-state buffer control end is valid, the data on the PIN will be transmitted to our SCM internal bus.

d latch : form a latch, usually with a sequential circuit, time series of the unit circuit learning digital Circuit we have known that a trigger can save a bit of binary number (that is, with hold function), in 51 microcontroller 32 root i/ A d trigger is used to form the latch in the O-Port line. Everyone fancy D latch, D end is the data input, CP is the control end (that is, the timing control signal input), q is the output, q is not the reverse output side.
For D flip-flops, when the D input has an input signal, if the control terminal CP is not signaled (that is, the timing pulse does not arrive), then the input D data is not transmitted to the output Q and reverse output Q non. If the timing pulse of the timing control CP is reached, then the data entered at the D end is transmitted to the Q and Q non-end. After the data is transmitted, when the timing signal of the CP Timing controller disappears, the output also maintains the data of the last input (that is, the last data is locked up). If the next sequence control pulse signal comes, then the D-end data is transmitted to the Q-terminal again, thus changing the status of the Q-terminal.

multi-channel switch : In the 51 microcontroller, when the internal memory is sufficient (that is, when the memory is not required for external expansion memory, which is described here, including data memory and program memory), the P0 port can be used as a common input and output ports (i.e. I/O), For 8031 (internal without ROM) or the program is written more than the internal memory capacity of the microcontroller, when external expansion of memory, the P0 port as an ' address/data ' bus use. Then this multi-channel selector switch is used to select whether it is used as a general I/O port or as a ' data/address ' bus. You see, when the multi-switch is connected with the following, the P0 port is used as a normal I/O port, when the multi-switch is connected with the above, the P0 port is used as the ' address/data ' bus.
Output Drive part : from which we have seen that the output of the P0 port is a push-pull structure consisting of two MOS tubes, that is to say, the two MOS tube can only lead one at a time, when V1 conduction, V2 on the cutoff, when V2 conduction, V1 cutoff.
and door, and non-gate : The logic principle of the two units circuit we have done in the fourth lesson number and common logic circuit has been introduced, do not understand the students back to the fourth section to see.
Before we have a detailed explanation of the unit parts of the P0, let's look at the specific working process of the P0 port as I/O port and address/data bus use.

1. How it works as an I/O port
When used as I/O port, the control signal of the multi-switch is 0 (low level), the fancy line part, the control signal of the multi-way switch is connected with one input of the gate at the same time, we know that the logic characteristic of the gate is "all 1 out of 1, 0 out of 0" then the control signal is 0, At this time with the gate output is also a 0 (low level), and let the output is the 0,V1 tube cutoff, in the multi-control switch control signal is 0 (low level), the multi-channel switch is connected with the latch of the Q non-terminal (that is, the P0 port as I/O port line use).

The P0 port is used as an I/O port, which is output from the data bus to the pin (that is, output state outputs) : When the write latch signal CP is active, Data bus signal → latch input d→ latch reverse output q non-terminal → multi-switch →v2 tube gate →v2 drain to output end p0.x. We have already said that when the control signal of the multi-switch is low-level 0 o'clock, and the gate output is low, the V1 tube is cut off, so as the output, P0 is open-drain outputs, similar to the OC Gate, when the drive on the current load, the need for the external pull-up resistor.

is the flow chart (red arrow) that outputs data to the P0 port from the internal data bus.

The P0 port is used as an I/O port line, which is input from the pin to the internal data bus (that is, input-state input) for the working process:

There are two cases of data entry (read P0 port)

1. Reading pin

Read the data on the chip pin, read PIN number, read pin buffer open (that is, the control of the tri-State buffer to be effective), through the internal data bus input, see (Red Simple head).

2. Read latch

Read the status of the latch output Q by opening the read latch tri-state buffer, see (red arrow):

In the input state, the signals read from the latch and from the pin are generally consistent, but there are exceptions. For example, when the low level is output from the internal bus, the latch q=0,q non =

1, the field effect tube T2 Open, the port line is low-level state. At this point, regardless of whether the signal on the port line is low or high, the signal read into the microcontroller from the pin is low so that the signal on the port pin can not be read correctly. Also, when the high level is output from the internal bus, the latch q=1,q non = 0 and the FET T2 cutoff. If the external pin signal is low, the signal read from the PIN is different from the signal read in from the latch. For this reason, 8031 microcontroller in the port P0 a P3 input operation, there are the following conventions: For this reason, 8051 microcontroller in the port P0 a P3 input operation, there are the following conventions: where the read-modify-write instructions, read the signal from the latch, the other instructions from the port Pin line read into the signal.
Read-Modify-write instruction is characterized by the input (read) signal from the port, after the operation (modification) within the microcontroller, and then output (write) to the port. Here are a few examples of read-modify-write instructions.

The reason for this arrangement is that the read-modify-write instruction needs to get the status of the port's original output, modify and then output, read the latch instead of the read pin, can avoid the external circuit for the reason of the original port state is read wrong. P0 Port is a 8031 MCU bus port, time-sharing data D7 a D0, low 8-bit address A7 an AO, and three-state, used for interface memory, external circuit and external equipment. The P0 port is the most widely used I/O port.

2. How it works as an address/data multiplexing port
The P0 port is used as the address/data multiplexing port when accessing external memory.
At this time, the multi-switch ' control ' signal is ' 1 ', ' with the door ' unlocked, ' and the gate ' output signal level is determined by the "address/data" line signal, the multi-channel switch and the output end of the inverter connected, the address signal by the "address/data" line → Inverter →v2 fet gate →v2 drain output. For example: The control signal is 1, the address signal is "0", with the gate output low level, V1 tube cutoff, inverter output high level, V2 pipe conduction, the output PIN address signal is low level.

See (blue font is level):

Conversely, the control signal is "1", the address signal is "1", "and gate" output is high, V1 tube conduction, inverter output low level, V2 tube cutoff, the output pin address signal is high. See (blue font is level):

Visible, in the output "address/data" information, V1, V2 tube is alternately conduction, load capacity is very strong, can be directly connected to the peripheral memory, no need to increase the bus driver. The P0 port is also used as a data bus. When the external program memory is accessed, the P0 port outputs a low 8-bit address information and becomes a data bus for reading the script (input).
During the fetch instruction, the "control" signal is "0", the V1 tube cutoff, and the multi-channel switch also follows the turn latch inverter output q non; the CPU automatically writes 0FFH (11111111, i.e. to the D latch to a high level ' 1 ') write to the P0 port latch, so that the V2 tube cutoff, under the Read PIN signal control, through the read pin three-state gate circuit to read the instruction code to the internal bus. Please look

If the directive is output data, such as Movx @DPTR, A (which transmits the contents of the accumulator to the external RAM via the P0 port data bus), the multi-switch "control" signal is ' 1 ', and the ' gate ' is unlocked, similar to the workflow of the output address signal, which is based on "address/data" Line → inverter →v2 field effect Tube Gate →v2 drain output.

If the instruction is an input data (read external data memory or program memory), such as Movx A, @DPTR (input the external RAM a storage unit content through the P0 port data bus into the accumulator A), the input data is still through the read PIN tri-State buffer to the internal bus, Its process is similar to the read script flowchart in.

The above analysis shows that when P0 is used as the address/data bus, the CPU automatically writes the 0FFH to the P0 port latch before reading the instruction code or inputting it, which destroys the original shape of the P0 port. Therefore, it can no longer be used as a generic I/O port. In the future, we must pay attention to the system design, that is, the program can no longer contain the P0 port as the operand (including the source operand and the purpose operand) instruction.

second, the structure and working principle of P1 Port
The P1 port has the simplest structure and is used only as a data input/output port. The output information is latched, and the input has a read pin and a read latch. See the structure of the P1 port.

As the diagram shows, the main difference between the P1 port and the P0 port is that the P1 port uses the internal pull-up resistor R instead of the P0 Port's Fet T1, and the output information is only from the internal bus. After the data output by the internal bus is reversed by the latch and the FET, the lock exists on the port line, so the P1 port is a static port with an output latch.
From the visible, to properly read the external information from the PIN, you must first turn off the FET so that the state of the pin is determined by the externally entered information. To do this, the port must be written to l before it can be read into the PIN. An input/output port with this operating characteristic is called a quasi-bidirectional I/O interface. 8051 single-chip microcomputer P1, P2, P3 are quasi-bidirectional port. P0 Port because the output has three-state function, before the input, the port line is already in high impedance state, no need to write l before the read operation. P1 the structure of the mouth is relatively simple, we have detailed analysis of the P0 mouth, as long as everyone seriously

Analysis of the working principle of P0 mouth, P1 mouth I think we all have the ability to analyze, here I do not much discussion.
After the microcontroller reset, each port has been automatically written to 1, at this time, can be directly input operation. If in the process of applying the port, has been to P1 a P3 port line output over 0, then to enter, you must write 1 and then read the pin before you can get the correct information. In addition, with the input instructions, the H port also has a read latch and read pin points.

three, the P2 port structure and working principle:

A structure of the P2 port is shown in:

The diagram shows that the P2 port has both a pull-up resistor on the chip and a switch MUX, so the P2 port features both the P0 port and the P1 port. This is mainly shown in the output function, when the switch is switched down, a data output from the internal bus is reversed by the inverter and the FET, the output is on the port pin line; When the multi-switch is up, an address signal from the output is also reversed by the inverter and the FET and is output on the port pin line. For the 8031 microcontroller must be the add-in memory to form an application circuit (or our application circuit extends the external memory), and the P2 port is used to periodically output the address from the external memory (high 8-bit address), so the P2 port of the multi-switch is always switching, The data from the internal bus and the address from the address signal line are output by time-sharing. So the P2 port is a dynamic I/O port. The output data is latched, but does not appear stably on the port line. In fact, the data output here is often an address, but a high 8-bit address for external RAM.
In terms of input functionality, the P2 port is the same as the P0 and H ports, with a read pin and a read latch, and the P2 port is also a quasi-bidirectional interface. Visible, the main features of the P2 port include: ① can not output static data;
The ② itself outputs the high 8-bit address of the external program memory;
When the ② executes the MOVX instruction, it also outputs the high address of the external RAM, so the P2 port is the dynamic address port.
That is, the P2 port can be used as I/O port, but also as a address bus use, below we do not analyze two of its working state.

1. Working process as I/O port is used
The P2 port can be used with an I/O port when there is no external program memory or if there is an external data memory, but is less than 256B, that is, when a high 8-bit address is not required (in this case, the external data memory cannot be read and written via the data address register dptr). At this time, the "control" signal is "0", multi-channel switch to latch the same phase output q, the output signal through the internal bus → latch phase output q→ inverter →v2 Tube Gate →V2 Tube 9 drain output.
Due to the V2 drain with a pull-up resistor, can provide a certain pull-up current, load capacity of about 8 TTL and non-gate; As an output, it is also necessary to write "1" to the latch, so that the inverter output is low, the V2 tube cutoff, that is, the pin is high on the fly, to prevent the pin from being clamped After the read pin is valid, the input information is read through the three-state gate circuit to the internal data bus.

2, as the address bus use of the work process
P2 Port as a address bus, "control" signal is ' 1 ', multi-way switch car to address line (that is, up), address information by inverter →v2 Tube gate → drain output. Since the P2 port outputs a high 8-bit address, unlike the P0 port, there is no need for time-sharing, so the address information on the P2 port (a15~a8 on the program memory) has a high 8-bit DPH save time and does not need to be latched.

IV. structure and working principle of P3 Port
P3 Port is a multifunctional port, it can be as I/O mouth, but also has a second function, P3 port of a structure see.

By visible, the P3 port and the PL port are structurally similar, except that there are two options for each port line of the P3 port. When the first function, the second output function line is 1, at this time, the internal bus signal through the latch and FET input/output, the role of the same as the P1 port, is also a static quasi-bidirectional I/O port. When in the second function, the latch output 1, through the second output function line to output a specific internal signal, in terms of input, that can be read through the buffer pin signal, but also through the substitution of input function to read into the specific second function signal on the chip. Since the output signal is latched and has a dual function, the P3 port is a static dual-function port. Special functions of the P3 port (i.e. the second function):

The conditions for making the P3 end product line in the second function are:

1. Serial I/O is in running State (RXD,TXD);

2, opened the department interrupted (INT0,INT1);
3. The timer/counter is in the external Count state (T0,T1)

4. Execute instruction to read and write external RAM (RD,WR)

In the application, if you do not set the P3 port of the second function (Wr,rd letter of the production without setting), then the P3 port line automatically in the first function state, that is, the static I/O port working state. In more cases, depending on the needs of the application, several port lines are set to the second function, while the other port lines in the first function of the running state. In this case, the P3 port should not be used as a byte operation, it should take the form of bit operation.

Port load capacity and input/output operations:
The P0 port is capable of driving 8 lsttl loads. To increase the load capacity, the bus driver can be added on the P0 bus. The P1,P2,P3 port can drive up to 4 lsttl loads. As mentioned earlier, since the P0-P3 port has been mapped to a P0 P3 port register in a special function register, the read/write of these port registers implements the input/output of the information from the corresponding port. For example:
MOV A, P1; input the information on the PL port line to a

MoV P1, A; the contents of a are output from the P1 port

MOV P3, #0FFH; make P3 port line each position L

In this lesson we have 51 single-chip microcomputer 4 8-bit parallel port with you to analyze, in the following chapters we will also work with the peripherals to learn from you.

Study Questions

1. Please analyze the working principle of D latch.
2, detailed description P0, P1, P2, P3 mouth work principle?
3. What are the second functions of P3 port? How is the second function allocated in practical applications?

C51 port structure and operating principle (RPM)