Connection between LUT and logic

 

I. principle and structure of a look-up table

 

The PLD chip with this structure can also be called FPGA, such as the acex, Apex, Spartan, and Virtex series of Altera.

Look-up-table (LUT) is essentially a ram. Currently, FPGA uses 4-input Lut, so each LUT can be regarded as a 16x1 RAM with 4-bit address lines. After you describe a logical circuit through a schematic or HDL language, the PLD/FPGA development software automatically calculates all possible results of the Logical Circuit and writes the results to ram in advance, each input signal performs a logical operation, which is equivalent to entering an address for table search, finding out the corresponding content of the address, and then outputting it.

The following is an example of 4 inputs and gates,

 

 

 

(Reproduced from: http://www.fpga.com.cn/advance/structures/lut.htm)

 

2. Connection Between LUT and logic in FPGA tutorial

 

Low Cost FPGA (For example Cyclone Series, Spartan Series) 4 Input Lut The table completes the combination logic, which is equivalent to 16bit Storage space, 4-bit address input, 1-bit Output Ram Through the Configurator 16bit To complete any " 4. Input and Output logical expressions " If necessary Out = ABCD (Four inputs and portals), the configuration data is "0x8000" , That is, when you find the address "4B '100" , Ram The output is 1 Otherwise, it is zero.

Assume that I need to implement a calculator and output its carry valueCarryWhich are represented by Logical Circuits and configuration data?

If we only have three input values,LutHow to complete the input?

In a digital circuit, there is a delay in signal transmission, and the delay is caused by the logic gate itself, because the transistor in the logic gate has a delay in signal transmission; latency is also produced by the distributed capacitance of the external circuit, so the output signal of the logic gate must lag behind the input signal.

The average and non-gate transmission delay time refers to the delay time for a digital signal to be input from the input end and output from the output end after passing through the door circuit. It reflects the speed of the circuit transmission signal.

 

For the convenience of testing, the average delay time is measured at the starting point of 1/2 of the voltage waveform swing. Raised edge from input50%To the output descent edge50%The resulting time is called the conduction delay time.TPHL; Drop edge from input50%To the output rising side50%The end time is called the end time.TPlh. The average value of the on-going delay time and the end delay time is called the average delay time (for example)

 

StandardTTLTypical approx.10ns.

Any digital electronic technology is based onTTLTechnology is evolving. Of course, today's digital technology usesCMOSTechnology-oriented, so itselfLutThere is also a delay from address input to storage value output, which also affectsFPGAAn important factor in the frequency of work, with the continuous advancement of technology, the delayFPGAWorking Frequency does not play a key role.

Now let's take a more complex example: Two32-bitData comparator:

From the logic expression, we need to do the following steps:

Temp [31 .. 0] = ain [31 .. 0] XOR bin [31 .. 0];

Equal = Not (temp [31] Or temp [30]… Or temp [1] Or temp [0]);

UseVHDLImplementation and useFPGAImplementation Method:

Library IEEE;

Use IEEE. std_logic_00004.all;

Use IEEE. std_logic_unsigned.all;

Use IEEE. std_logic_arith.all;

 

Entity comparator_32b is

Port (

Ain: In std_logic_vector (31 downto 0 );

Bin: In std_logic_vector (31 downto 0 );

Equal: Out std_logic;

Great: Out std_logic

);

End comparator_32b;

 

Architecture synlogic of comparator_32b is

Begin

Equal <= '1' When ain = bin else '0 ';

-- Great <= '1' When ain> bin else '0 ';

End synlogic;

You can see in the comprehensive report that it requires21Logical resources (namelyLutSuch:

 

Description"Great <= '1' When ain> bin else '0 ';"?

After the above descriptions, we can know FPGA According to the logic function you describe, the logic is divided into several steps to make them suitable Lut And then Lut Generate configuration data and connect each Lut To complete the logic function. Maybe you can see from { Temp [31 .. 0] = ain [31 .. 0] XOR bin [31 .. 0] equal = Not (temp [31] Or temp [30]… Or temp [1] Or temp [0]) } To Lut Although they all perform the same function, there is a big gap from the logic gate they consume. If we use a logical expression directly, we need 31 Items XOR Door, 30 Items Or And each Lut Each Bit Equivalent 4 Portal, that is 4 Portal /Bit ; So FPGA Yes 21*16*4 From the logic cost. FPGA Not like ASIC Mass production, FPGA So that it allows you to make mistakes in the design, unlike ASIC After the stream piece is released, it cannot be modified, and the cost of each stream piece has reached 100 Tens of thousands of dollars ( 65nm ), Is the cost that small and medium-sized enterprises cannot afford, if the wrong design into the market, the resulting maintenance costs are even more difficult Estimation, for example, NVIDIA One-time expenditure in the second quarter 1.96 $, Used to address the previous generation of some models used for laptops MCP (Media communication processor) and GPU (Graphics processor) Products " Insufficient core and packaging materials " ; Thus FPGA Popular in many professional fields.

 

(Reproduced from: http://blog.ednchina.com/wind330/194115/message.aspx)

 

2. logical unit and gate correspondence of FPGA

 

Generally, there are two calculation methods for FPGA equivalent gate number. One is to compare the basic FPGA unit (such as LUT + ff, ESB/Bram) with the standard gate array that implements the same function, the number of gate contained in the gate array is the equivalent number of the FPGA basic unit. Then, multiply the number of basic units to obtain the FPGA gate number estimation value; the second is to use FPGA and the standard gate array to implement the same function, and calculate the equivalent number of FPGA doors. This method relies heavily on empirical data.

For the first method, when FPGA includes LUT/FF/Ram and other resources, when analyzing the number of equivalent resources, the general principle is equivalent, that is, to implement the same function, the gate number required in a standard gate array is the equivalent gate number of FPGA resources. For example, to implement a 4-input XOR with register output, A lut and a FF must be used in FPGA, in standard gate arrays, 21 and non-gate implementations are generally used, so one LUT + 1 FF is equivalent to 21. For ESB (Bram), because four ports are required to implement 1 bit Ram using a standard gate array, 1 bit is equivalent to four ports when Sb/barm is used for Ram, for a 2048bit ESB in Altera FPGA, the equivalent number of doors is 8 K. This data alone cannot accurately calculate the equivalent number of FPGA ports. This is only a simple situation, and the actual situation is much more complicated.

For example, if we implement 2 input XOR with register output, FPGA also needs 1 LUT + ff, while the Standard gate array only needs 8 NAND, therefore, one LUT + one FF is equivalent to eight. At the same time, the implementation of specific functions requires different numbers of doors in different standard gate arrays. Therefore, the calculation of equivalent doors can only be a approximate value. That is to say, the estimation of the number of FPGAs of a specific model is closely related to the use of FPGA resources. LUT is used to implement two input XOR and four input XOR equivalent numbers (respectively 1 and 13 ); FF without asynchronous resetting, resetting, clock enabling, and the number of equivalent doors with these ports are different (8 and 13 respectively); When ESB (Bram) is used for Ram, 1 bit is equivalent to 4 doors, and 1 2048bit Bram is equivalent to 8 K doors. However, when using a search table, it may be less than 200. Therefore, it is necessary to make more detailed analysis to estimate the number of equivalent FPGA doors.

The following uses ep20k1000e as an example to describe the estimation method of FPGA's equivalent number of doors.

(1) Calculate the equivalent number of logical Arrays
When estimating the number of ep20k1000e doors, compare FPGA-specific resources with the number of LSI lca300k Data Books of the lca300k standard logical array to estimate FPGA equivalent doors. Fpga lut + FF equivalent number of Gate 2 shows

That is, LUT + FF is equivalent to 8 ~ The upper and lower thresholds are defined by simple functions and complex functions respectively.

The equivalent number of apex20k can also be obtained based on empirical data. FPGA is used to implement more than 100 designs targeting 4-input Lut, and lca300k gate arrays and Design Compiler are also used, comparing the number of Le used by FPGA with the number of lca300k, we can see that each Le is equivalent to 12. Ep20k1000e has 38400 le, which is equivalent to 0.46 million.

(2) Calculate the equivalent number of ESB doors
The number of doors required by a bit in Ram is related to the ram architecture, process, and manufacturer. Generally, 1 bit is equivalent to four doors, and Altera also adopts this standard, this allows you to easily estimate the number of equivalent ESB doors.

You can also use the LSI lca300k method to calculate the equivalent number of ESB doors, that is, by comparing the number of doors used to achieve the same capacity of RAM in lca300k, you can get the equivalent number of each bit of ESB, to calculate the number of equivalent ESB doors, see Figure 3.

4 gates/bit is a suitable estimate, so the equivalent number of ESBs in ep20k1000e is 160 ESBs x 2,048 bits per ESB x 4 Gates per bit = 1,310,720 gates, that is, about 1.3 million gates.

All in all, for ep20k1000e, the number of LUT + FF equivalent doors is about 0.46 million (empirical value), and the number of equivalent doors for full use of ESB as Ram is about 1.3 million, so the maximum number of system doors is 1.7 million.

Conclusion:
The FPGA equivalent gate number estimation method can be to compare the basic elements of FPGA resources (such as LUT + ff and ESB) with the standard gate arrays that implement the same functions to obtain the equivalent gate numbers of FPGA basic elements, multiply the number of units to get the equivalent number of FPGA. It can also implement many designs, and calculate the number of equivalent doors in comparison to the standard gate array.

The estimation of FPGA's equivalent number of doors is generally divided into two parts: LUT + ff and ESB (Bram). LUT + FF is equivalent to 8 ~ 21 doors, with a typical value of 12. When using an ESB for Ram, it is generally equivalent to 4/bit. At this time, the maximum number of doors is estimated, if the ESB performs product/Lut, the number of equivalent doors is greatly reduced. For example, for ep20k1000e, the former is 1.3 million, and the latter is 20 thousand.

 

(Reproduced from: http://blog.mcuol.com/User/luozhen0810/Article/9646_1.htm)