Conversion of VHDL Data Types

In the VHDL program, different types of objects cannot be substituted, So type conversion is required. The conversion methods include:
(1) type TAG method. Use the type name to implement
Conversion.
Example: variable X: integer;
Variable Y: real;
You can use the value assignment statement to convert a type by using the type tag (that is, the type name:
X: = INTEGER (y); y: = real (X ).
(2) type function method.
A variety of conversion functions are provided in the VHDL package, so that some types of data can be converted to each other to achieve correct value assignment operations. common types of conversion functions include:
★Conv_integer (): converts the std_logic_vector type
Integer type.
★Conv_std_logic_vector (): returns the integer type, unsigned
Type or signed type to std_logic_vector type.
★To_bit(): Converts the std_logic type to the bit type.
★To_bit_ Vector (): converts the std_logic_vector type
Bit_vector type.
★To_std_logic (): converts the bit type to the std_logic type.
★To_std_logic_vector (): converts the bit_vector type
Std_logic_vector type.
Note: you must first open the library and the corresponding package when referencing.
This function is composed of std_logic_unsigned
Package Definition
This function is composed of std_logic_arith
Package Definition
The following functions are composed of std_logic_1164

-0 -----------------------------------------------

Type conversion
Variable number of class types
ByStd_logic_ Vector to integer
Std_logic_ Unsigned include set
Conv_integer ()
Converted from integer, unsdgned, signedStd_logic_ Vector
Convert from unsigned and signed to integer
Std_logic_ Arith package set
Conv _Std_logic_ Vector (A, bit length)
Conv_integer ()
ByBit_ VectorStd_logic_ Vector
ByStd_logic_ VectoBit_ Vector
ByBitConvertStd_logic
ByStd_logicConvertBit
Std_logic_ 1164 package set
To_stdlogicvector ()
To_bitvector ()
To_stdlogic ()
To _Bit()
Merit
Letter count
By"Std_logic_ Vector "converts an instance to an integer.
Library IEEE;
Use IEEEStd_logic_ Ipv4.all;
Use IEEEStd_logic_ Unsigned. All;
Entity add5 is
Port (Num: InStd_logic_ Vector (2 downto 0 );
Bytes
);
End add5;
Architecture RTL of add5 is
Signal in_num: integer range 0 to 5;
Bytes
Begin
In_num <= conv_integer (Num); bit vectors are converted to integer transformations.
Bytes
End RTL;
^ 0 ^

------------------------

Letter Quantity Name Merit Yes

Std_logic_1164 package set

To_stdlogicvector (a) is converted from bit_vector to std_logic_vector

To_bitvector (a) is converted from std_logic_vecto bit_vector

To_stdlogic (a) is converted from bit to std_logic

To_bit (a) is converted from std_logic to bit

Std_logic_arith package set

Conv_std_logic_vector (A, converted by integer, unsdgned, signed

Bit Length) std_logic_vector

Conv_integer (a) is converted from unsigned and signed to integer.

Std_logic_unsigned include set

Conv_integer (a) is converted from std_logic_vector to integer.

 

 

N library IEEE;

N use IEEE std_logic_00004.all;

N use IEEE std_logic_unsigned.all;

N entity add5 is

N port (Num: In std_logic_vector (2 downto 0 );

N Branch

N );

N end add5;

N architecture RTL of add5 is

N signal in_num: integer range 0 to 5;

N Branch

N begin

N in_num <= conv_integer (Num); bit vectors are converted to integer transformations.

N Branch

N end RTL;

Conversion of VHDL Data Types