Enable 4GB physical memory address addressing in real mode (called Big Real mode)
- Modify the data of the 0x90 port via the A20 fast Gate, place it (similar to opening a switch) and turn on
- Shutting down external interrupts using CLI assembler directives
- System data structures required to load protection mode using LGDT
- Set the value of the CR0 register to turn on protection mode
- Enter protection mode
- Reloads the data in the FS register so that it supports addressing of the physical memory address of 4GB
- Immediately set the data-off protection mode of the CR0 register
- Using the STI Assembler command to open an external interrupt
- This allows the CPU to support 4GB addressing.
- Note: This big Real mode is necessary, we need to load the kernel code to more than 1MB of physical memory address space, then we need to turn on 4GB memory addressing, the reason is to return to the real pattern is because all memory addresses in real mode is accessible, and in protected mode can not, Here we need to access some physical addresses so we need to return to real mode
mode switch after kernel code is loaded and moved to a location above the specified 1MB
- The A20 quick door switch has been opened in Big Real mode and is not needed here.
- Manual initialization of the GDT data structure (including: Segment Descriptor (data segment and code snippet), segment selector (used to index data segment and code snippet), the base address and length of the GDT (this is loaded into the GDTR register via the LGDT assembly instruction))
- Manually initializing a good IDT data structure
- Shutting down external interrupts using CLI assembler directives
- Use LGDT to load the base address and length of the data structure defined above into a register
- The value of the set (PE) CR0 Register turns on protection mode
- Enter protected mode to execute instructions at 0 privilege level
- Using the JMP directive to point the CPU to protected mode code
- Code for CPU Execution Protection mode
- The next step is to enter into the ia-32e mode (64-bit)
Enter ia-32e mode
- Determine if the CPU supports IA-32E mode, if supported (see steps below)
- Manually initializing a 64-bit GDT
- Reload GDT, Lgdt to GDTR
- Data-off paging mechanism for CR0 registers PG
- Data PAE-Open Physical Address Extension (PAE) for CR4 registers
- ia-32e mode for the LME sign-position of the set-Ia32_efer register
- Data-opening paging mechanism for CR0 registers PG
- Using JMP to point the CPU to the kernel code
CPU mode switching involved in the loader program
