[FPGA] FPGA configuration (as, PS, JTAG)

FPGA configuration Changjiang scholar 2007-11-23 09:51:29 Tags: I record my campus knowledge/exploration

A lot of brothers for CPLD under the download of JTAG is very familiar with, can turn to FPGA when, more or less confused, how to appear the configuration chip, why to use different download cable, different download mode? I'm going to talk about some personal insights about something I know. Concurrent with some data. I want to pass by a friend to drink a pick, moderator to point prestige. There are problems we also discuss together, welcome to shoot bricks.
1.FPGA devices have three types of configuration download: Active configuration mode (as) and passive configuration mode (PS) and most commonly used (JTAG) configuration methods. As by the FPGA device boot configuration operation process, it controls the external memory and initialization process, the EPCs series. For example, the EPCS1,EPCS4 configuration device is dedicated to the as mode and currently only supports the Cyclone series. This is done using the Altera serial configuration device. Cyclone during the period of active status, the configuration period in a subordinate position. The configuration data is fed into the FPGA via the DATA0 pin. The configuration data is synchronized on the DCLK input and 1 clock cycles transmit 1 bits of data. (See attached drawings)
PS The configuration process is controlled by an external computer or controller. This is done through configuration devices such as the Enhanced Configuration device (EPC16,EPC8,EPC4), where the configuration data is stored externally from the external storage unit and fed into the FPGA via the DATA0 pin during the PS configuration. Configuration data on the DCLK rising edge latch, 1 clock cycles transmit 1 bits of data. (See attached drawings)
The JTAG interface is an industry standard, primarily used for features such as chip testing, using the IEEE STD 1149.1 federated Boundary Scan Interface PIN, which supports the Jam STAPL standard and can be done using the Altera download cable or the master controller.
When the FPGA is working properly, its configuration data is stored in SRAM and must be re-downloaded when power is added. In an experimental system, a computer or a controller is usually used for debugging, so PS can be used. In the practical system, in most cases, the FPGA must be actively guided to configure the operation process, when the FPGA will actively from the peripheral dedicated storage chip to obtain configuration data, and this chip in the FPGA configuration information is designed by the ordinary programmer in the POF format of the file into. Dedicated configuration device: EPC model Memory Common Configuration device: epc2,epc1,epc4,epc8,epc1441 (now seems to have been phased out) for Cyclone Cycloneii series devices, Altera also provides configuration devices for the as mode, EPCs series. If the EPCS1,EPCS4 configuration device is also serial configured. Note that they apply only to the Cyclone series. In addition to the single bit configuration such as AS and PS, some devices now support parallel configuration such as Pps,fps, which improves configuration speed. Of course, the plug-in circuit and PS have some differences. There are processor configuration such as Jrunner and so on, if you need to Baidu it, at least 10 kinds. For example, Altera Company's configuration mainly has Passive Serial (PS), Active Serial (AS), Fast Passive Parallel (FPP), Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial Asynchronous (PSA), JTAG and other seven configuration methods, wherein Cyclone support configuration has ps,as,jtag three kinds.
2 on the FPGA chip configuration, you can use the As mode method, if the use of EPCs chip, through a download line for burning, then the beginning of the "Nconfig,nstatus" should pull up, if you consider a variety of configuration mode, you can use jumper design. Let configuration in the jumper switch, the resistance of the pull-up resistor can be used 10K 3, in PS mode tip: If you use the Cable configuration board FPGA chip, and this FPGA chip has a configuration chip on the board, then you must isolate the cable and configuration chip signal. (Cheung See). General debugging will not put on the configuration chip welding, this time with the cable download program. Only after the debugging is done, the program is burned in the configuration chip, and then the chip is soldered. Or the configuration of the chip is easy to remove the kind of welding. This is a problem and can be easily debugged. &<60; In the AS mode tip: Use a board as a download, configuration chip has been welded on the board, the original as mode in the configuration chip with the cable to download, will automatically prohibit the configuration of the FPGA, and PS mode needs to be isolated on the circuit.
4, usually with JTAG configuration epc2 and flex10k, and then EPC2 with PS configuration flex10k. This is better. (This is what I see on the Internet, can you use it?) 5, download cable, Altera under the download cable is divided into Byteblaster and BYTEBLASTERMV, as well as Byteblaster II, and now also released based on Usb-blaster. Because BB is basically already very few people use, And Usb-blaster is now too expensive, here is the difference between Bbii and BBMV. BBII support multi-voltage power supply 5.5v,3.3v,2.5v,1.8v; The BBII supports three download modes: As, which can be programmed for Altera's as serial configuration chip (EPCs series) &<60; &<60; &<60; &<60; &<60; &<60; &<60; &<60; &<60; &<60; PS, can be configured for FPGA &<60; &<60; &<60; &<60; &<60; &<60; &<60; &<60; &<60; JTAG, programmable on FPGA,CPLD, Altera configuration Chip (EPC series) &<60; &<60; and BBMV only support PS and JTAG 6, generally do FPGA test board, (such as Cyclone series), with the As+jtag way, so you can use JTAG debugging, and finally the program has been debugged, then use as mode to burn the program to the configuration chip, And this has a clear advantage, is that when the as mode can not be downloaded, the quartus comes with the tool to generate JTAG mode can be used in the JIC file to verify that the configuration chip is damaged, the method is attached (this is Chun-long people wrote, from our jar, if there is a copyright issue, inclusion). 7.Altera FPGA can be configured by SCM, CPLD and so on, the main principle is to meet the datasheet in the timing can, here I do not say, interested friends can see the following articles, should be able to understand what is going on. 8. When configured, the Quartus software Operation section: (1). assignment-->device-->device&Amp;pin options--> Select configuration scheme,configuaration mode,configuration device, note
Configuration mode is not selectable for machines that do not support remote and local updates, and configuration devices produce POF files based on different
If selected automatically, the device with the minimum density is selected and suitable for the design (2). You can define the function of the two-port pin after configuration, in just Device&pin option-->dual-purpose pins--> You can continue when the configuration is complete i/ O-Port
Use (3). There are also a lot of hook-up options under the General menu, which are generally not changed by default, see Altera Configuration
Handbook,volume2,sectionii. (4) The scope of application of the file with different suffix name: sof (SRAM Object file) when directly using PS mode to use the configuration data in the FPGA, USB BLASTER,MASTERBLASER,BBII,BBMV applicable, quartusii will be self-
All other configuration files are generated by SOF. POF (Programmer Object File) is also automatically generated by quartusii, bbii applicable, as mode under the configuration data to the configuration chip in the RBF (Raw binary file) for the microprocessor binary files. In Ps,fpp,pps, The use of the PPA configuration in the RPD (Raw programing Data file) contains bitstream binary files, can be configured as mode, can only be generated by the POF files hex (hexadecimal file) This is not much said, the microcontroller in a lot of TTF ( Tabular Text File) for Fpp,pps,ppa, and bit-wide PS configuration mode SBF (Serial bitstream file) to configure Flex 10k and Flex6000 Jam (Jam File) in PS mode Used specifically for the use of Program,verigy,blank-check JIC 6 floor has been mentioned, here is not much to say
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[FPGA] FPGA configuration (as, PS, JTAG)