FPGA static timing Analysis--io Port timing (Input delay/output Delay) (reproduced)

Reprint Address: http://www.cnblogs.com/linjie-swust/archive/2012/03/01/FPGA.html1.1 Overview

In high-speed systems, FPGA timing constraints include not only internal clock constraints, but also full IO timing constraints and timing exception constraints for PCB board-level timing closure. Therefore, the timing constraints of IO ports in FPGA timing constraints are also an important point. Only when the constraints are correct can the FPGA and external devices communicate correctly at high speed.

1.2 FPGA integral concept

Since IO port timing constraint analysis is for timing analysis of the entire system of the board, the FPGA needs to be analyzed as a whole, including FPGA settling time, hold time, and transmission delay. The traditional settling time, hold time and transmission delay are all for the analysis of register form. However, the settling time for the entire system FPGA can be simplified.

Figure 1.1 FPGA overall timing diagram

As shown in 1.1, the performance parameters for the decomposed FPGA internal registers are:

(1) The Tdin is the delay from the IO port of the FPGA to the internal register input of the FPGA;

(2) The TCLK is the delay from the IO port of the FPGA to the clock end of the FPGA internal register;

(3) tus/th is the settling time and holding time of FPGA internal register;

(4) TCO for FPGA internal register transmission time;

(5) Tout for the output from the FPGA register output to the IO port delay;

For the entire FPGA system analysis, these parameters can be redefined: The FPGA settling time can be defined as:

(1) FPGA settling time: Ftsu = Tdin + tsu–tclk;

(2) FPGA hold time: FTh = Th + tclk;

(3) FPGA data transfer time: Ftco = tclk + Tco + Tout;

From the above analysis, when the FPGA becomes a system, the IO timing analysis can be done. The FPGA model changes to 1.2.

Figure 1.2 FPGA system parameters

1.3 Input Maximum minimum delay

The external device sends the data to the FPGA system model 1.3 shown. The input maximum minimum delay constraint on the IO port of the FPGA is to allow the FPGA design tool to optimize the path delay between the input port and the first level register as much as possible, so that the system clock can reliably pick up the signal from the external chip to the FPGA.

Figure 1.3 FPGA data input model

The input delay is the time delay from the external device sending data to the FPGA input port. These include clock source to FPGA delay and delay to external devices, data transmission TCO through external devices, plus trace delay on PCB. 1.4, for external devices and FPGA interface timing.

Figure 1.4 External device and FPGA interface timing

1. Maximum input delay

Maximum input delay max (Lanuch edge) with maximum external device clock skew (TCLK1), maximum device data output delay (TCO), and maximum PCB trace delay (TPCB) when transmitting from the data clock edge The delay of timing satisfaction is also ensured by subtracting the minimum FPGA clock offset (Ftsu). In order to ensure the FPGA settling time, the accurate acquisition of this data value, that is, the setup slack must be positive, 1.1, the calculation formula as shown in the following form:

Setup slack = (tclk + Tclk2 (min)) – (Tclk1 (max) +tco (max) +TPCB) +ftsu

The following formula is introduced:

TCLK1 (max) + TCO (max) + TPCB (max) –tclk2 (min) ≤tclk + Ftsu

The official Altera data sheet informs:

Input delay max = Board delay (max) –board clock Skew (min) + Tco (max)

In combination with the system parameter formula is:

Input delay max = TPCB (max) – (Tclk2 (min) –tclk1 (max)) + Tco (max)

2. Minimum input delay

The minimum input delay time (input delay min) is the minimum external device clock skew (TCLK1), the minimum device data output delay (TCO), and the minimum PCB trace delay (TPCB), when the data is sent from the clock edge (Lanuch edge). At this time the total delay value must be greater than the FPGA maximum clock delay and settling time of the sum, so as not to destroy the FPGA last data retention time, that is, hold slack must be positive, 1.1, the formula is shown as follows:

Hold slack = (TCLK1 (min) + Tco (min) + TPCB (min)) – (FTh + TCLK2 (max)) ≥0

The following formula is introduced:

Tclk1 (min) + Tco (min) + tpcb (min) –tclk2 (max) ≥fth

The official Altera data sheet informs:

Input delay max = Board delay (min)-Board clock Skew (min) + Tco (min)

Combined with this system parameter formula is

Input delay max = TPCB (min) – (TCLK2 (max) –tclk1 (min)) + Tco (min)

It is learned from Equation 4 and equation 8 that we need to estimate 4 values for the calculation of the maximum input minimum delay:

(1) External device output data through the PCB board to reach the maximum and minimum value of the FPGA port TPCB,PCB delay experience value of 600mil/ns,1mm = 39.37mil;

(2) The maximum and minimum TCO of the output data delay after the external device receives the clock signal;

(3) The clock source reaches the external device's maximum and minimum clock skew Tclk1;

(4) The clock source reaches the maximum and minimum clock skew Tclk2 of the FPGA;

When the external device clock is provided for the FPGA, the TCLK1 and TCLK2 are synthesized as shown in the tshew,1.5:

Figure 1.5 FPGA output Clock model

1.4 Output Maximum Minimum delay

The FPGA output data is shown in external device model 1.6. The output maximum minimum delay constraint on the IO port of the FPGA is to allow the FPGA design tool to optimize the path delay between the first register and the output port as much as possible, so that the external device can accurately capture the output data of the FPGA.

Figure 1.6 FPGA output delay model

The output delay is the delay time when the data is output from the FPGA to the external device. These include clock source to FPGA delay and delay to external devices, trace delay on PCB board, and data setup and hold time for external devices. As shown, interface timing diagram for FPGA and external devices.

Figure 1.7 FPGA output delay

1. Maximum Output delay

The official Altera data sheet informs:

Output Delay max = Board delay (max) –board clock Skew (min) + Tsu

It is learned from the formula that the maximum output delay (outputs delay max) is the maximum PCB delay, the smallest FPGA and device clock skew after being emitted from the FPGA data, plus the settling time of the external device. Constrained maximum output delay, is to constrain the IO port output, so that the external device data settling time, that is, the setup slack must be positive, the formula is as follows:

Setup slack = (tclk + Tclk2 (min)) – (Tclk1 (max) +ftco (max) +TPCB) +tsu

The formula is deduced as follows:

Ftco (max) + TPCB (max) – (Tclk2 (min) –tclk1 (max)) +TSU≤TCLK

Again, the following formula is obtained:

Ftco (max) + Output delay MAX≤TCLK

Thus, the maximum constraint output delay, that is, to inform the compiler FPGA Ftco maximum value, according to this value to make the correct synthesis results.

2. Output minimum delay

The official Altera data sheet informs:

Output delay min = Board delay (min) –board clock skew (max) –th

It is known from the formula that the minimum output delay (outputs delay min) is the minimum PCB delay, maximum FPGA and device clock skew after being emitted from the FPGA data, minus the settling time of the external device. Constrain the minimum output delay, is to constrain the IO port output, so that the IO port output has a minimum delay value, to prevent the output is too fast, destroy the external device last clock data retention time, resulting in a negative hlod slack, can not be properly latched to the data, the minimum output delay deduction calculation formula as shown in the following equation:

Hold slack = (TCLK1 (min) + Ftco (min) + TPCB (min)) – (Th + TCLK2 (max)) ≥0

The formula is deduced as follows:

Ftco (min) + TPCB (min) – (TCLK2 (max) –tclk1 (min)) –th≥0

Again, the following formula is derived:

Ftco (min) + Output delay min≥0

It is known from the formula that the maximum constraint output delay, that is, to inform the compiler FPGA Ftco minimum value, according to this value to make the correct synthesis results.

It is learned from Equation 10 and equation 14 that we need to estimate 4 values for the calculation of the maximum minimum delay of the output:

(1) FPGA output data through the PCB board to reach the external device input port maximum and minimum TPCB,PCB delay experience value of 600mil/ns,1mm = 39.37mil;

(2) The clock source reaches the external device's maximum and minimum clock skew Tclk2;

(3) The clock source reaches the maximum and minimum clock skew Tclk1 of the FPGA;

(4) The settling time of external devices Tsu and holding time th;

When the external device clock is provided for the FPGA, the TCLK1 and TCLK2 are synthesized as shown in the tshew,1.8:

Figure 1.8 FPGA provides a clock model

1.5 Scope of Use

Through author usage summary, IO port timing constraints are mainly used in the following situations:

1. High frequency of data exchange

Since IO timing constraints generally calculate values in a few nanoseconds, when the FPGA and external data exchange frequency is low, such as FPGA operation 640*480 TFT LCD brush screen, data transmission frequency is only 24Mhz, a data clock has 41.666ns, completely without constraints can meet the timing requirements. However, when the operation SDRAM run to 120M, because a data transformation period of 8ns, so a small number of IO port delay will affect the SDRAM data, so in this case, the input and output needs to complete the IO port timing constraints, and analysis is correct, in order to eliminate the data transmission instability.

2. The code is more optimized

When the frequency of data exchange is high, but timing constraints do not meet the timing requirements, we need to analyze the code, good timing is designed, not constrained. As shown in Listing 1.1, the first Hcount_r and Vcount_r are 10-bit counters, so that the code TFT three-color output port will have a great delay, because dat_act the glue logic too much, the output path is too long caused. In this case, the timing constraints should not be the first time, you should modify the code, as far as possible register direct output. Only when the code is optimized, do the timing constraints to get better results.

Program Listing 1.1 sample program

1 Assign Dat_act  =    ((hcount_r >= hdat_begin) && (Hcount_r < hdat_end))              
2 && ((Vcount_r >= vdat_begin) && (Vcount_r < vdat_end));
3 Assign Tft_r    =    (dat_act)? {Rgb16_dat[15:11], 3 ' b111}: 8 ' h00;
4 assign Tft_g    =    (dat_act)? {Rgb16_dat[10:5],  3 ' b111}: 8 ' h00;  
5 assign Tft_b    =    (dat_act)? {rgb16_dat[4:0],   

1.6 Summary

This document is mainly to the FPGA IO port timing constraints of the corresponding analysis, did not do the actual use of analysis, in subsequent documents will be combined with the software, as well as the actual case of the IO port timing constraints For detailed use of the introduction. Finally, I enclose an example of Altera's official IO timing constraint analysis, as shown in 1.9.

Figure 1.9 Altera official routines

FPGA static timing Analysis--io Port timing (Input delay/output Delay) (reproduced)