GNU make summary (iii)

First, makefile variables

The variable names in makefile are case-sensitive, such as "foo" and "foo" are two different variables. Generally, for general variables , we can use lowercase, and for parametric variables , all uppercase. This variable is used in the form of "$ (variable_name)" or "${variable_name}" when we define the good one variable. Any use of "$" in a command or file name requires two "$$" to represent it. The expansion of a variable can be seen as a macro expansion in the C language and a text substitution process.

1 two ways to define variables

1.1 Recursive expanded variables

use "=" or "define." definition, which is treated as a text substitution process when used. The so-called recursive expansion is that when a variable is defined, it does not expand, but when the variable is used, the content that it refers to will be expanded in layers. The Advantage is that when a variable is defined, you can reference a variable that was not previously defined (a variable that might be defined later in the section or passed by the Make command-line option), and the disadvantage is that recursive calls can occur and fall into a dead loop.

1.2 Direct Expansion Variables

Use the ": =" definition. In this way, references to other variables are expanded when defined, so you cannot reference subsequent defined variables. In more complex makefile, use this approach to define variables to reduce the chance of error.

Note: When using direct expansion, you can implement a leading space in a variable, as follows:

NullString: =space:end of the line

The space variable represents a space, with a space between the comment and $ (nullstring).

Note, however, that the trailing spaces are not ignored when make handles variables.

In the case of a variable definition, if the variable is not previously defined, the variable is assigned a value, otherwise the value of the variable remains unchanged, and this operation can be done by "? =" .

2 Use of Variables

"$ (var:a=b)" means that all words ending with a in variable VAR are replaced with a word ending in B (the so-called "word" is a different string separated by a space). The other parts of the variable remain unchanged.

Like what:

Foo: = A.O b.o c.Obar:= $ (foo:. O=.C)

After the substitution, the content of the variable bar is A.C B.C c.c

Another variable substitution uses the "patsubst" function. The pattern character% needs to be used, as shown below:

Foo: = A.O b.o c.Obar:= $ (foo:%.o=%.c)

When you use a variable that is not defined, make defaults to its null value.

Some special variables have fixed values in make, but we can also explicitly re-assign values to them.

3 Append Variable Value

If you want to append a value to an existing variable, you can use the "+ =" operation, as follows:

Object = MAIN.O foo.o bar.o utils. o   + = ANOTHER.O

Thus, the value of the object becomes: MAIN.O foo.o bar.o utils.o another.o

4 override indicator

When you execute make, the command line takes precedence over the definition in the makefile file, which means that if a variable is defined by the command line, it overrides the definition of the variable with the same name that appears in makefile. If you do not want the variables in the makefile to be replaced by the values passed by the command line, you need to use override to declare the variable as follows:

Override var = value or: override var:=+ = more

Note: If you previously defined a variable with override, you must use override when appending the variable, otherwise the append operation will not take effect. The purpose of using override is not to adjust the conflict of command line arguments and makefile variables, primarily to specify invariants for some requirements I. For example, the "-g" option must be used at compile time, so we can define the Cflags as follows:

Override CFLAGS + =-G

This allows us to ensure that the "-g" option persists regardless of which parameters are passed in the command line.

5 multi-line definition

The define indicator defines a variable that contains a multiline string. The format is as follows:

Define Lines Echo Foo Echo $ (bar)Endef

Start with define, Endef end. Lines is the variable name, and the middle is the variable value.

If the variable lines is executed as a command package, it is equivalent to:

"lines = echo foo; echo $ (bar) "

Note: variable values can include: line breaks, whitespace, tab, and so on. If you start with tab, the row is processed as the command line.

6 System Environment Variables

Any system environment variables that have already been defined can be used in makefile. If an existing system environment variable is redefined, the make execution process uses the user-defined variable value, unless the "-e" option is used at make, at which point the user's definition does not overwrite the system environment variable with the same name.

By default, all system environment variables and command-line arguments are passed to the child make process, and if you need to pass a normal variable to the child make, you need to declare the variable with an "export" designator.

Note: The system environment variable "SHELL" is special and is used as an interface between the user and the system, so this variable is reset in make to "/bin/sh".

7 Target specified variable

A target specifies that the scope of a variable is the context of all these targets, including all execution procedures related to the target, with "locality". The format is as follows:

TARGET ...  ...: override Variable-assignment

Variable-assignment is an assignment expression, you can use "="/": ="/"+ ="/"=".

Specifying a specific value for a variable affects only the target associated with it, and the remaining targets are unaffected.

The target specifies that the variable has the same priority as the normal variable, and therefore may be affected by command-line arguments, which require the use of the "-e" option or override.

The target specified variable and global variable with the same name belong to two different variables and can have different definition styles.

8 pattern specified variable

When you use a target to specify a variable definition, this variable is defined on the target of a specific target and the rule it is causing. The pattern specifies that the variable definition assigns a variable value to all targets that conform to this pattern. Set a pattern to specify the variable as follows:

PATTERN ...  ...: override Variable-assignment

The pattern here uses the pattern character%, such as%.A,%.O, compared to the target specified variable. If% is used alone as the target, the specified variable is valid for all types of targets.

Second, makefile command

A rule's commands are made up of some shell commands, which are executed in a single line. In addition to the first command that is separated by semicolons after the dependency list, the other command lines must start with the tab character.

There can be blank lines and comment lines between multiple command lines, but Note: if a blank line starts with the Tab key, it is not a normal blank line, but an empty command line.

Often there may be multiple different shells in the system, and if not explicitly specified, the command line in all rules is parsed using "/bin/sh".

1 echo of command

In general, make will display the command itself to the standard output device before executing the command. However, if the command line starts with "@", then the Echo function before execution is canceled. For example:

@echo begin ...

Show at execution: Begin ...

If "-N" or "-just-print" is passed in the command line when make is executed, make will simply echo the command to be executed, including the command starting with "@" instead of executing the commands. With this option, we print out all the commands that need to be executed in the makefile in the order in which they are executed.

Conversely, make's "-S" or "--silent" will prohibit the display of all execution commands, equivalent to all commands starting with "@".

2 execution of the command

Rule, the command defined by this rule will be executed when the target needs to be rebuilt. In the case of multiple-line commands, each row of commands is executed using a separate child shell process (that is, the execution of multiple lines of command is independent of multiple processes and no dependencies exist).

Multiple commands written in the same line in Makefile belong to a full shell command line, and are ultimately executed as a separate shell process. Therefore, if you want to use a CD to enter a directory in makefile, and then execute a command under that directory, you must write the CD as a shell command line, and the CD execution has no effect on subsequent commands, as follows:

foo:bar/lose    CD Bar, gobble lose >. /Foo can also: Foo:bar/lose    cd bar; \    >. /foo

3 Concurrent Execution Commands

Typically, the next command executes only after the current command has been completed. If you need make to execute multiple commands at the same time, you can use "-j" or "--job". "-j" can be followed by an integer that tells the compiler how many commands are allowed at the same time, called "Job Slots", with a default value of 1, which indicates that make will execute the rule serially.

Note: There may be multiple commands simultaneously reading the standard input at the same time, but the standard input device can only have one process access to it at the same time, when the operating system emits a pipe burst signal.

When you execute make, if a command fails and the error generated by the command cannot be ignored, other command executions that are used to reconstruct the same target will be terminated. At this point, if make does not use the "-K" or "-keep-going" option, do will stop execution and exit. However, if make is about to be terminated and its child processes are executing, make must wait until all of these child processes have ended before actually exiting.

When you perform make, if the system is overloaded, you need to control the system load that the make program consumes, use the "-L" or "-max-load" option, followed by a floating-point number, such as-l 2.5 Tell the Make program to not start any subroutines that execute commands when the average system load exceeds 2.5. The "-l" without floating-point number is used to cancel the "-L" set earlier. There is no load limit by default.

4 Command Execution Error

Typically, when a command in a rule finishes running, make checks the return status of the command execution and, if it succeeds, starts another child shell process to execute the next command. Sometimes, a command execution failure does not indicate a rule execution error. In order to ignore the failure of the command execution, you can precede the command with "-", for example:

Clean :    -rm *. O

Indicates that make will continue to execute even if the RM delete file fails.

Using the command-line option "-I" or "-ignore-errors" while executing make can also ignore all command execution errors.

5 make the interrupt

If you receive a fatal signal when you execute a command, make will delete the target files for those rules that have been rebuilt in the process, ensuring that the target file will be rebuilt correctly the next time that makes. Assuming you are compiling FOO.C, you receive a "CTRL + C" signal, but you may have started creating foo.o at this point, just not done. If you do not delete foo.o, the next time you perform make, the FOO.O is not rebuilt because the timestamp of the FOO.O is newer than foo.c, so the incorrect destination file is obtained.

Of course, if the target file exists only to record the command execution time, then the target file should not be deleted, the target file can be used as. Precious, the file will not be deleted even if make terminates unexpectedly.

6 make the recursive execution

The process by which make executes the command itself or executes other makefile files is called recursive execution of make. Recursive invocation is useful in a multilevel directory where, for example, there is a "subdir" subdirectory in the current directory that contains a makefile file that you need to start from the current directory and compile for all subdirectories when you perform make:

Subsystem:     CD subdir && $ (make)

Indicates that the SubDir directory is first entered and then the make work is performed under that directory.

Note: The value of the variable make is "make".

7 variables and recursion

During the recursive execution of make, the upper-level make can explicitly specify that the definition of some variables is passed to the child make process through the environment variable, but it does not overwrite the variable with the same name as defined in the makefile file executed by the child make process. Use the variable definition in child make, unless you are using the "-e" option of make.

If you need to pass the makefile variable in the upper make process to the child make process, you need to declare the variable as export, which will add the variable to the environment variable as follows:

Export VARIABLE ...

If you do not want to pass a variable to the child make, you can use the Unexport declaration, as follows:

Unexport VARIABLE ...

Note: for both shell and makeflags variables, they are always automatically passed to the child make process during the entire make execution unless they are declared with Unexport.

Using the variables or functions declared by export and Unexport, they are immediately expanded at the point of declaration.

If export does not take any variables, it means that all variables defined in this makefile are passed to the child make process, but a unexport without any parameter variables is meaningless.

In the Make program for multilevel recursive calls, the variable makelevel represents the depth of the call. During the execution of make, the value of the makelevel is constantly changing, at the top level of 0, at the next level of 1, ..., which is primarily used in conditional test commands.

8 command-line options and recursion

The command line option "-K" "-S" for upper make is automatically passed to the child make process via the environment variable MAKEFLAGS. Similarly, variable definitions in the command line, such as make CFLAGS + =-G, are also passed to the child make process with the environment variable MAKEFLAGS.

Note: The following command line options are not assigned to Makeflags: "-C" "-F" "-O" "-w".

When performing a multi-level make call, if you do not want to pass makeflags to the child build process, you need to leave it empty when you call the sub-make, as follows:

Subsystem:     CD

This also cancels the inheritance of the parent make command-line option when child make executes.

9–w Options

In a multi-level make call, the option "-W" or "-print-directory" allows you to give relevant hints before you start compiling a directory and after you finish compiling the directory, so that developers can track the execution of make. Of course, many options are automatically added with the "-W" parameter when they are executed. If you want to suppress the printing of directory hints, you can use the "-S" option or the command-line option "-no-print-directory".

Ten Defining Command Packages

If many different rules use the same set of commands, it is convenient to define this set of commands as a command package, similar to a function or method. Use define to complete this function in the following format:

Run -YACC$ (firstword $^) mv y. TAB.C $@endef 

Where RUN-YACC is the command package name, the middle is the command body. Variables and functions in the command body are not expanded until they are used.

Use as follows:

Foo.c:foo. y     $ (run-YACC)

One Empty Command

In executing the Make program, it is sometimes necessary to block makes to find the implied command for the rebuild target, which can be done using the null command. For empty commands, it is best not to have any dependent files.

You can use the following format:

Target:;

or a separate empty command line, but the command line must start with the tab character. This is generally not recommended because empty command lines and blank lines look no different.

GNU make summary (iii)