Intel's micro-architecture development history

Intel's micro-architecture development history (mik@mouseos.com)

I think: If you can understand Intel's CPU micro-architecture development history is always good. I have collected some data here. Thank you for the main sources.Wikipedia

1. Tick-tock

In 2007, Intel proposed Intel's future development model on CPU micro-architecture.Tick-tockMicro-arcitecture:

• TickUpdate and modify the previous micro-architecture. Typically, when a more advanced process is used and the micro-architecture is improved, the overall micro-architecture will not change significantly.
• TockIt refers to the release of a new generation of micro-architecture, but it will continue with the previous micro-architecture process, the new process will wait for the coming of the next tick pace.

The Tick-tock is like a clock swing action. The left side is tick, the right side is tock, And the tick-tock action is very vivid.

The following is a list of tick-tock development models proposed by Intel:

Architecture change		Architecture code	Process	Release Date	Application processor
					Fever level	Desktop	Mobile	Released CPU
Tick	New Process	Presler, cedar mill, Yonah	65nm	2006-01-05	Presler	Cedar mill	Yonah	Core Pentium
Tock	New Architecture	Core		2006-07-27	Kentsfield	Conroe	Merom	Core 2 Pentium dual-core
Tick	New Process	Penryn	45nm	2007-11-11	Yorkfield	Wolfdale	Penryn
Tock	New Architecture	Nehalem		2008-11-17	Bloomfield	Lynnfield	Clarksfield	Core I3 Core I5 Core i7
Tick	New Process	Westmere	32nm	2010-01-04	Gulffown	Clarkdale	Arrandale
Tock	New Architecture	Sandy Bridge		2011-01-09	Sandy bridge-ex	Sandy bridge-dt	Sandy bridge-Nb
Tick	New Process	Ivy bridge	22nm	2012
Tock	New Architecture	Haswell		2013

It can be seen that the tick-tock rhythm is updated every year. nehalem microarchitecture has been used for more than a year to release the new microarchitecture. Currently, we areSandy BridgeMicro-architecture, Next GenerationIvy bridgeThe architecture was improved based on Sandy bridge and used
22nm process. The new generation of micro-architecture will begin in 2013HaswellMicro-architecture

2. micro-architecture list

Starting from 8086, Intel officially started the development of X86 processor. The following is the x86 processor micro-architecture family starting from 8086:

1. 8086: 1st x86 Processor
2. 186: Added DMA controller, interrupt controller, timer, and chip select chips.
3. 286: Added protected mode.
4. I386: 1st generation 32-bit x86 Processor
5. Iworkflow: 2nd generation 32-bit x86 processor, with floating point units and pipelines added
6. P5: 1st-generation Pentium processor, after intel released multiple P5 microarchitecture pentiume1996ReleasedMMXTechnical Pentium processor
7. P6: P6 micro-architecture family is used on multiple subsequent Pentium micro-architecture, including:
   • Pentium Pro: Pentium Pro is a 6th-generation x86 processor released on1995.11, Pentiume pro is a new microarchitecture different from Pentium processor. It has added new features, including out of order execution and PAE (physical address extension ).

     More importantly, an additional decoding stage is added to the Pentium Pro pipeline to dynamically decode x86 commands into a series of micro operations (Micro-operations), These micro-ops are composed of a series of lower-LayerMicro-Instructions(Or microcode) to execute more complex x86 native commands. These microcode sequences can be re-ordered for analysis and distributed to various execution units.

   • Pentium II,Pentium II Xeon: Pentium II is based on pentiume pro, but has made major changes. The released pentiume II code is:
     • Klamath: belongs to family 6 and model 3 in the Intel processor family.
     • Deschutes: the Pentium Xeon processor is based on this code, which belongs to family 6, model 5
     • Tonga: mobile platform processor, belonging to family 6, model 5
     • DIXON: a mobile platform processor. It belongs to family 6 and model 6.
   • Pentium III,Pentium III Xeon: It is based on P6 microarchitecture, similar to Pentium, addedSSECommand:
     • Katmai: released on1999.05
     • Coppermine: released on1999.10
     • Coppermine T: This is a transitional product released on2001.06
     • Tualatin: released on2001Year
     • Tanner: Pentium III Xeon Platform Based on Katmai
     • Cascades: Pentium III Xeon Platform Based on Coppermine
   • Pentium M,Enhanced Pentium M: Based on the improved P6 micro-architectureSse2Instruction Set
     • Banias: released on2003.03
     • Dothan: released on2004.06
     • Yonah: belongs to enhanced Pentium M. SupportedSse3Instruction Set, released on2006
8. Netburst: P68 in the 7th generation micro-architecture, used on Pentium 4, Pentium D, and some Xeon, supported from Pentium 4Sse2,Sse3Instruction Set, added hyper-Threading Technology
   • Willamette: the initial version of pentiume 4, supportedSse2Instruction Set, released on2000.11
   • Northwood: released on2002.01
   • Gallatin: Used in the Pentium 4 EE processor. It supports hyper-Threading Technology and is released on2003.09
   • Prescott: released on2004.02, Start to supportSse3Instruction Set
   • Prescott 2 M: released on2005.02, Starting to support x86-64 Technology
   • Cedar mill: released on2006.01And supports the virtualization technology.
9. Core: The new generation of micro-architecture is based on the repeatedly improved P6 micro-architecture. It is an upgraded version of Yonah and isMulti-coreMicro-architecture, supportSsse3Instruction Set, addedMacro-ops FusionTechnology (Merge two x86 commands into one micro-ops), From
   Starting with core micro-architecture, Intel proposed a tick-tock development model. Core micro-architecture isTockThat is, the new architecture. The Code Penryn belongs to the tick, that is, the new process. The 45nm process is used:
   • CoreMicro-architecture: Uses 65nm, which belongs to the tock rhythm, that is, the new architecture.
     • Merom: mobile platform
     • Conroe: desktop platform
     • Kentsfield: fever level
     • Allendale: Xeon Platform
     • Conroe: Xeon Platform
     • Woodcrest: Xeon Platform
     • Kentsfield: Xeon Platform
     • Clovertown: Xeon Platform
     • Tigerton: Xeon Platform
   • PenrynMicro-architecture: Same as core micro-architecture, it uses a 45nm tick rhythm, that is, a new process, which is supported from Penryn micro-architecture.Sse4.1Instruction Set
     • Penryn: mobile platform
     • Wolfdale: desktop platform
     • Yorkfield: fever Platform
     • Wolfdale-Cl: Xeon Platform
     • Wolfdale: Xeon Platform
     • Yorkfield-6M: Xeon Platform
     • Yorkfield: Xeon Platform
     • Yorkfield-Cl: Xeon Platform
     • Harpertown: Xeon Platform
     • Dunnington: Xeon Platform
10. Nehalem: The New Generation of micro-architecture, used in core i7/I5/I3 processors, nehalem has added some new technologies, including:
    • Integrated Memory Controller supports 2, 3, and 4-channel memory
    • Integrated integrated graphics processor
    • To-point processor interconnected bus:QPI(Quickpath Interconnect)
    • Integrate PCI Express and DMI (direct media interface)

    Let's take a look at the development history of this generation of micro-architecture:

    • Nehalem:2008.11.17Release, which belongs to the tock rhythm, that is, the new architecture, uses the 45nm process of the previous generation and supportsSse4.2Instruction Set
      • Clarksfield: mobile platform
      • Lynnfield: desktop/Xeon Platform
      • Bloomfield: fever/Xeon Platform
      • Gainestown: Xeon Platform
    • Westmere:2010.01.07Release, which belongs to the tick pace, that is, the new process, using the 32nm process, supportsAES(AES-NI) Instruction Set andPclmulqdqCommand to start supporting1gPage)
      • Arrandale: mobile platform
      • Clarkdale: desktop platform
      • Gulftown: fever/Xeon Platform
      • Westmere-EX: Xeon Platform
      • Westmere-EP: Xeon Platform
11. Sandy Bridge: Up to now, the latest micro-architecture is used on the second generation of core i7/I5/I3 processors and improved on the previous generation of micro-architecture, each memory channel and each cycle can perform two load/store operations, support the next generation of SIMD command avx instruction set, and can execute a 256-bit vector operation, starting from Sandy bridge micro-architecture, no separate R & D code
    • Sandy Bridge: Belongs to the tock rhythm and follows the 32nm process of the previous generation,2011.01.09Release
      • Extreme/high-end: high-end platform core i7 extreme
      • Performance: Mainstream performance platforms include core i7 2600/K/S series, core I5 2500/K/S/T series, and core I5 2400 series.
      • Mainstream: Mainstream entry series core I3 series and Pentium series
      • Sever: Server Platform Xeno E5 series and Xeon E3 Series
      • Mobile: mobile platform core i7/I5/I3 Series
    • Ivy bridge: It is a tick, and the 22nm process will be used.2012Annual release
12. Haswell: The Next Generation of micro-appseture, which is expected to be approximately2013Year