Makefile of files in the batch compilation directory

1. Multiple c files generate the makefile of their respective executables
If there are many C files in a directory, and each C file can generate a standalone executable file, then you want to compile all of these C files and generate the executable files, in this directory to write a makefile file, you can do it. #定义所需变量
C = gcc
CFLAGS =-wall-o-g-o #编译链接-O
SRCs =$ (wildcard *.c)
Objs =$ (Patsubst%.c,%,$ (SRCS))
. Phony:all Clean
all:$ (OBJS)
%:%.c
$ (CC) $ (CFLAGS) [email protected] $<
Clean
Rm-f $ (OBJS)
Execute make to get:
Cc-wall-o-g-o Hello hello.c
Gcc-wall-o-g-o Unixio unixio.c
...  ... （

In the makefile rule, the wildcard character is automatically expanded . However, when the variable is defined and the function is referenced, the wildcard character is invalidated. In this case, if a wildcard is required to be valid, the function "wildcard" is used, and its usage is: $ (wildcard PATTERN ...). In makefile, it is expanded to a list of all files that already exist, separated by spaces, that match this pattern. If there are no files that conform to this pattern, the function ignores the pattern character and returns NULL. It is important to note that in this case, the expansion of the wildcard character in the rule and the previous section match the difference of the wildcard character.

Generally we can use "$ (wildcard *.c)" To get a list of all the. c files under the working directory. Use "$ (patsubst%.c,%.o,$ (wildcard *.c)") to get a list of. c files under the working directory using the "wildcard" function, followed by the suffix of all filenames in the list. C is replaced by. O. This allows us to get a list of the. o files that can be generated in the current directory. Therefore, in one directory, you can use the following makefile to compile all the. c files under the working directory and finally connect them as an executable file:

#sample Makefile

Objects: = $ (Patsubst%.c,%.o,$ (wildcard *.c))

Foo: $ (objects)

Cc-o Foo $ (objects)

Here we use the implicit rules of make to compile the. C source file. The assignment of a variable also uses a special symbol (: =).

1. Wildcard: Extended wildcard character
2. Notdir: Remove Path
3. PATSUBST: Replace wildcard characters

Example:
Set up a test directory to create a subdirectory named sub in the test directory
$ mkdir Test
$ CD Test
$ mkdir Sub

Under test, create A.C and B.c2 files, and in sub directory, create SA.C and SB.C2 files

To build a simple makefile
src=$ (wildcard *.c./sub/*.c)
dir=$ (Notdir $ (src))
obj=$ (Patsubst%.c,%.o,$ (dir))

All
@echo $ (SRC)
@echo $ (dir)
@echo $ (obj)
@echo "End"

Execution Result Analysis:
First line output:
A.C B.C./sub/sa.c./SUB/SB.C

Wildcard all files that have the suffix C under the specified directory./and./sub/are expanded.

The second line of output:
A.C B.C sa.c SB.C
Notdir the expanded file to get rid of the path information

The third line of output:
A.O B.O SA.O SB.O

In $ (Patsubst%.c,%.o,$ (dir)), Patsubst replaces the variable in the $ (dir) with the suffix of. c. O,
Any output.
Or you can use
obj=$ (DIR:%.C=%.O)
The effect is the same.

Here is the replacement reference rule in Makefile, which replaces another variable with the variable you specify.
Its standard format is
$ (var:a=b) or ${var:a=b}
What it means is to replace each value in Var with b by the end of a

Today, when studying makefile, I read an article on the Internet, and introduced the method of using the function wildcard to get all the C language source program file names under the specified directory, so that we don't have to manually specify a. c file that needs to be compiled, as follows:

SRC = $ (wildcard *.c)

equals the specified compilation of all. c files under the current directory, and if there are subdirectories, such as the Subdirectory, Inc, add a wildcard function like this:

SRC = $ (wildcard *.c) $ (wildcard inc/*.c)

You can also specify the assembler source program:
ASRC = $ (wildcard *. S

）

(i) Outer makefile

[HTML]View Plaincopyprint?

2. Subdirs = cell-renderer-spin \ #文件夹名
4. Custom-cell-renderer \
6. Custom-list-model \
8. custom-list-model-sorted \
10. Hello-world \
12. Simple-list \
14. Treeview-demo
18. All: $ (subdirs)
20. For dir in $ (subdirs); Do\
22. CD $dir && make && cd ... \ #批量编译
24. Done \
28. Clean: $ (subdirs)
30. For dir in $ (subdirs); Do\
32. CD $dir && make clean && cd ... \
34. Done
36. Rm-f ' Find-name "*~" | | /bin/true

(ii) Inner makefile

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1. CC = gcc
3. OBJS = MAIN.O CUSTOM-LIST.O
5. CFLAGS =-g-o2 ' pkg-config--cflags gtk+-2.0 '
7. Customlist: $ (OBJS)
8. Gcc-o customlist $ (OBJS) ' Pkg-config--libs gtk+-2.0 '
10. Clean
11. RM $ (OBJS) Customlist 2>/dev/null | | /bin/True

Reference: http://blog.csdn.net/sunbaigui/article/details/6718268

Makefile of files in the batch compilation directory