Makefile variable Assignment

When defining the value of a variable, we can use other variables to construct the value of the variable, and in makefile there are two ways to define the value of the variable with a variable.

The first way, that is, simply using the "=" number, the left side of the "=" is a variable, the right side is the value of the variable, the value of the right variable can be defined at any place in the file, that is, the right side of the variable is not necessarily a defined value, it can also use the value defined later. Such as:

Foo = $ (bar)
Bar = $ (ugh)
Ugh = Huh?

All
echo $ (foo)

We execute "make all" will be typed the value of the variable $ (foo) is "Huh?" The value of ($ (foo) is $ (bar), the value of $ (bar) is $ (ugh), and the value of $ (ugh) is "Huh?" Visible, variables can be defined using the following variables.

There are good places and bad places for this function, and the good part is that we can push the real value of the variable to the back to define it, such as:

CFLAGS = $ (include_dirs)-O
Include_dirs =-ifoo-ibar

When "CFLAGS" is expanded in the command, it will be "-ifoo-ibar-o". But this form also has a bad place, that is, recursive definition, such as:

CFLAGS = $ (CFLAGS)-O

Or:

A = $ (B)
B = $ (A)

This allows make to go into infinite variable expansion, and of course, our make is capable of detecting such a definition and will give an error. What's more, if you use a function in a variable, that way makes our make run very slow and, worse, he will use the two make function "wildcard" and "shell" to cause unpredictable errors. Because you don't know how many times these two functions will be called. http://hovertree.com/menu/linux/

To avoid this approach, we can use another method in make to define variables using variables. This method uses the ": =" operator, such as:

x: = foo
Y: = $ (x) bar
x: = Later

It is equivalent to:

Y: = foo bar
x: = Later

It is worth mentioning that this method, the preceding variable cannot use the following variables, can only use the previously defined variables. If this is the case:

Y: = $ (x) bar
x: = foo

So, the value of y is "bar", not "foo bar".

Here are some simple variables to use, let's take a look at a complex example, including the use of make functions, conditional expressions, and a system variable "Makelevel":

Ifeq (0,${makelevel})
Cur-dir: = $ (shell pwd)
WHOAMI: = $ (Shell whoami)
Host-type: = $ (Shell arch)
Make: = ${make} host-type=${host-type} Whoami=${whoami}
endif

As for the conditional expressions and functions, we'll say later, for the system variable "makelevel", which means that if our make has a nested execution (see the previous "nesting use make"), then this variable will record the number of calls to our current makefile.

Let's take a look at an example, if we want to define a variable whose value is a space, let's say that we need to know about the two variables defined here:

NullString: =
Space: = $ (nullstring) # End of the line

NullString is an empty variable, where nothing is, and the value of our space is a space. Because it is difficult to describe a space on the right side of the operator, the technique used here is very useful, first using an empty variable to indicate the value of the variable, and then using the "#" notation to denote the termination of the variable definition, so that we can define a variable whose value is a space. Note here about the use of "#", The Notation "#" which deserves our attention if we define a variable like this:

Dir: =/foo/bar # directory to put the frobs in

Dir The value of this variable is "/foo/bar", followed by 4 spaces, if we use such a variable to specify a different directory-"$ (dir)/file" then it is finished.

There is also a more useful operator is "? =", first look at the example:

FOO? = Bar

The implication is that if Foo is not defined, then the value of the variable foo is "bar", and if Foo was previously defined, then the phrase will do nothing, which is equivalent to:

Ifeq ($ (Origin FOO), undefined)
FOO = Bar
endif

Recommendation: http://www.cnblogs.com/roucheng/p/3470287.html

Makefile variable Assignment