Simulation is an indispensable step in IC design, and it is necessary to record the waveform file for detailed analysis and research. Say a few waveform files Wlf (wave Log file), VCD (Value change Dump) file, Fsdb (Fast Signal DataBase) file, SHM, VPD:
1, for WLF waveform log file, as long as we have used Modelsim, should be very familiar. WLF (wave Log file) is a waveform file supported by Mentor Graphics company Modelsim. But when we look at waveforms in the waveform window, a *.wlf file is generated at the end of the simulation (the default is Vsim.wlf). Next time we can open this saved waveform directly via Modelsim. Vsim-view vsim.wlf-do run.do where the content of run.do is the waveform signal to be viewed. It is emphasized that this WLF file can only be generated by Modelsim and can only be displayed by Modelsim. is not a common file file format.
2. VCD (Value change Dump) is a common format. VCD files are an ASCII file defined in the IEEE1364 standard (Verilog HDL language standard). It mainly contains the header information, the variables of the predefined and variable value of the change information. It is because it contains the signal change information, it is equivalent to record the entire simulation information, we can use this file to reproduce the simulation, we can display the waveform. Because VCD is part of the Verilog HDL language standard, all Verilog emulators are capable of implementing this feature, as well as allowing users to dump VCD files through system functions in Verilog code. We can generate waveforms by Verilog HDL's system function $dumpfile, which specifies the data of certain modules and signals in the simulation by $dumpvars parameters.
In particular, it is precisely because the VCD records the complete change of signal information, we can also use a VCD file to estimate the design of power consumption, which is not available in other waveform files. Both the encounter and PrimeTime PX (Prime power) can be used for power analysis via the input network file, a library file with power consumption information, and a VCD file generated after simulation.
Because VCD is part of the Verilog HDL language standard, all Verilog emulators need to be able to implement this feature. So we can use the system function to dumpvcd the file in the Verilog code. In addition, we can use the Modelsim command to dump VCD files, which can be extended to VHDL. Specific commands: VCD file MYFILE.VCD
VCD add/test/dut/* This generates a VCD data message with all the signals under the DUT.
We're using it to simulate Vsim-vcdstim myfile.com
Or join in the Testbench:
3, Fsdb (Fast Signal DataBase) is the spring Soft (Novas) company Debussy/verdi support waveform files, generally smaller, more widely used, the rest of the simulation tools such as Ncsim, Modlesim, etc. you can dump FSDB files directly by loading Verdi PLI (typically located under the Share/pli directory in the installation directory). The Fsdb file is Verdi uses a proprietary data format, similar to a VCD, but it is only a useful information to signal the simulation process, removing the information redundancy in the VCD, like the VCD data for a Huffman encoding. Therefore, the FSDB data volume is small and the simulation speed is increased. We know that VCD files are implemented using Verilog built-in system functions, and FSDB is implemented through the Verilog PLI interface. $fsdbDumpfile, $fsdbDumpvars, etc.
Its aftermath of the file is different simulation or debugging tools support file types, non-universal, but the basic can be converted from a VCD file (in fact, the compact version of the VCD file, because only to take the simulation debugging required data, so the file size is much smaller than the original VCD file), Some also provide the function of mutual conversion with VCD files.
4. SHM is a waveform file supported by the Cadence company NC Verilog and Simvision, in fact. SHM is a directory that contains. DSN and. TRN two files.
5, VPD is Synopsys company VCS DVE support waveform files, can be produced with $vcdpluson.
By using Cadence NC Verilog to compare the same testcase and the same dump waveform conditions, the shortest time to produce the Shm file (nonsense, originally a company), the time to produce a VCD file is as many times as the SHM and Fsdb. In the author's test example, the resulting Fsdb file is dozens of MB for the more than 10 Mb,shm file, and the VCD file is a few gigabytes in size.
Some uses of Fsdb:
(1) The following is a list, prompting the fsdb of the various possible uses, the specific content we can Google A, they are out.
Fsdbdumplimit-How do I limit the size of fsdb files to use?
$fsdbDumpvars ([<level>], <scope | signal>*)
Fsdbdumpfile-Specify FSDB file name
$fsdbDumpfile ("<fsdb name>")
Fsdbdumpvars-dump the specified variable
Fsdbdumpsingle-dump the specified signal
Fsdbdumpvariable-dump the specified VHDL variable
Fsdbswitchdumpfile-Switch dumping to another FSDB file
$fsdbSwitchDumpFile ("<new FSDB name>")
Fsdbautoswitchdumpfile-Limit file size and automatically create a new Fsdb file when the amount of data is too large
$fsdbAutoSwitchDumpfile (<file size>, "<fsdb name>",< number of file>)
Fsdbdumpflush-force to Dump Result to FSDB file
Fsdbdumpmem-dump the contents of the specified memory
$fsdbDumpMem (<reg name>, [<start Addr>, [<size>]])
$fsdbDumpon-Open FSDB dumping
$fsdbDumpoff-Close FSDB dumping
(1) A free-switching Fsdb method
Sometimes it takes a long time to run a simulation, but the wave of care is just a small part of it. This time how to switch waveforms, so that the file is not too large? A method is described here. Examples are for reference only, and you can create more diverse changes in combination with practical applications.
Conditional expression 1
Conditional Expression 2
(2), we are more commonly used in general and $value$plusargs this task, in the Test_top:
$value $plusargs ("casename=%s", Casename)
Pass the Casename through the script at run (to Vcs/nc sim_arg: +casename= $Testcase _name.fsdb)
It is easy to dumpfsdb at the same time if you run multiple testcase at the same time, and also to skip some time to start
Dump (sim_arg: +time= $start _time)
$value $plusargs ("time=%d", skip)
(3), project everyone concerned about the module different, in order to frequently modify the Test_top dump, will also be the need to dump the content with Dumplist
File to implement the
such as dump.list content #用于注释)
When you use it, you usually add the relevant statement to the TEST_TOP.V:
reg [100:0] casename;
Integer skip, I;
if ($test $plusargs ("Dumpfsdb")) begin
if ($value $plusargs ("time=%d", skip))
if ($value $plusargs ("casename=%s", Casename))
$fsdbAutoSwitchDumpfile (Casename, 30);
$fsdbAutoSwitchDumpfile ("./test_top.fsdb", 40);
When running simulation, if you want to start the dump waveform at 5000ns (time unit root timescale), give VCS/NC parameters
+dumpfsdb +time= +casename= Testcase1.fsdb
The TESTCASE1 generally we will associate with the case name after the script is processed, and this will start from 5000 when we run out of the way.
Testcase1_000.fsdb, testcase1_001.fsdb like this,
2. The other dump.list (name can be taken casually) inside the setting is the same as the normal set dump level settings.
Hierarchical path name
Dump FSDB Wave
reg [8*30*-1:0] waveform_name;
Start_dump = 0;
Finish_time = 0;
Waveform_name = "Debussy.fsdb";
if ($test $plusargs ("FSDB"))
if ($test $plusargs ("Dump_file"))
result = $value $plusargs ("dump_file=%s", waveform_name);
Select dump Signals
Methods for generating various waveform files Vcd,vpd,shm,fsdb