Modelsim Primary Use Tutorial

Modelsim Beginner's tutorial (GO) I. Introduction of Modelsim

The Modelsim simulation tool was developed by model company. It supports Verilog, VHDL, and their hybrid simulations, which can step through the entire program, allowing the designer to see directly the next statement that his program will execute, and to see the current value of any variable at any point in the program's execution. The dataflow window can be used to view the continuous changes of input and output of a cell or module, which is more powerful than the Quartus simulator, and is one of the most common emulators in the industry.

For beginners, Modelsim's own tutorial is a good choice in Help->se PDF documentation->tutorial. It tells the use of Modelsim in detail from simple to complex, from low to advanced. Easy to understand. But it also has shortcomings, it is all the cases in which the initial preparation work has been placed in the example folder, directly add them to the Modelsim can be used, it is assumed that the user of the current operation of the pre-preparation work is already familiar, so beginners often do not know how to do the current operation of the pre-preparation.

Second, installation

As with many other software, Modelsim SE also requires legal license, and usually we use Kengen to generate License.dat.

1 Unzip the installation Kit to start the installation, select Full product installation when installing. Select No when install Hardware Security Key driver appears. When the Add Modelsim to Path option is present. Select Close when the Modelsim License Wizard appears.

2 Create a new folder in the C packing directory FLEXLM, generate a License.dat with keygen, and then copy it to the folder. If the license is passed, but the open Modelsim still goes wrong, the system time is set to 2008, regenerate the license, and then the time is transferred back.

3 Modify the environment variables of the system. Right click on the desktop My Computer icon, properties---Advanced environment variable---(System variable) new. Fill in the contents of the variable value if there is already another path, please use ";" Separate it from the path you want to fill. Lm_license_file = C:\flexlm\license.dat

4 installation is complete and can be run.

Note: 1, the user name of the computer can not be Chinese;

2, installation path can not appear in Chinese and space, can only have numbers, English letters and underscore "_" composition;

3, if the computer also needs to use Modelsim-altera 6.4a (Quartus II 9.0), do not need to do any additional settings, Modelsim SE 6.3g will automatically catch this system variable, and use this license file, and vice versa.

Figure 1 Setting the environment variables required for Modelsim (user)

PS : Establishing links between Quartus II and Modelsim

① will need to set Modelsim path in Quartus II after completion of the above work, Quartus II menu Tools-->general-->eda Tool Options, related settings, such as Modelsim:c:\model As shown in Tech_6.3g\win32 2.

Figure 2 Setting the Modelsim path

② set up the Modelsim as a simulation software or in the Assignments-->eda Tool settings when building the Quartus II project.

three, Modelsim simulation method

Modelsim simulation is divided into pre-simulation and post-simulation, the following is a detailed description of the difference between the two.

3.1 Pre-simulation

Pre-simulation is also called functional simulation, the main purpose is to verify that the function of the circuit meets the design requirements, which is characterized by not considering the circuit gate delay and line delay, mainly verifying that the circuit is consistent with the ideal condition. The integrated FPGA code is described in RTL-level code language, and its input is RTL code and testbench.

3.2 Post-simulation

Post-simulation is also called time series simulation or layout and post-routing simulation, refers to the circuit has been mapped to a specific process environment, considering the circuit delay and the impact of the gate delay, verify whether the circuit can meet the design concept under a certain timing conditions, there is a timing violation. The input file is a gate-level grid that abstracts from the layout results, Testbench, and a standard latency file with an SDO or SDF extension. The standard delay files of SDO or SDF include not only the gate delay, but also the actual wiring delay, which can better reflect the actual operation of the chip. In general, after simulation is required, check the design timing and actual FPGA operation is consistent, to ensure the reliability and stability of the design. After the device assignment pin has been selected, the simulation is done.

basic steps for 3.3 Modelsim simulation

The simulation of Modelsim is mainly in the following several steps:

(1) Set up the library and map the library to the physical directory;

(2) Compile the original code (including Testbench);

(3) perform the simulation.

The above 3 steps are large frames, both pre-simulation and post-simulation are carried out according to this framework, and the establishment of MODELSIM engineering is not necessary for front-to-back simulation.

3.3.1 Building a library

Create a separate folder before performing a simulation, and the subsequent operations are performed under this file to prevent accidental operation between files. Then start Modelsim to modify the current path to the folder, and modify the method by File->change directory Select the newly created folder to see.

Figure 3 Creating a new Folder

When doing pre-simulation, it is recommended to create a new folder as described above.

After the simulation, a folder will appear under the Quartus II project folder: Project folder \simulation\modelsim, provided that the correct compilation of Quartus II works; Therefore, no new folders need to be created.

The emulation library is the directory that stores the compiled design unit, there are two kinds of emulation libraries in Modelsim, one is the working library, the default library name is work, the other is the resource library. The work library contains all the files that have been compiled under the current project. So you must build a work library before compiling, and can only build a work library. The resource library holds the resources that are called to the files that have been compiled in the work library, so there may be many resources that are placed in different repositories. For example, to do a post-simulation of a design that is integrated in a cyclone chip, a resource library called Cyclone_ver is required.

The mapping library is used to map the directory of pre-compiled files to a Modelsim recognizable library, the files within the library should be compiled, the libraries should be visible in the workspace window, and if the files are not compiled, they are invisible in the library.

There are two ways to build a simulation library. One is in the user interface mode, point File->new->library appears the following dialog box, select a New library and a logical mapping to it, in the library name enter the name of the library to be created, and then OK, You can generate a new library that is already mapped. Another way is to enter the following command in the transcript window:

Vlib work

Vmap work

Figure 4 Building a simulation library

If you want to delete a library, simply select the library name and right-click to select Delete.

It is important to note that you should not manually create a library or add files to the library in a system disk outside of Modelsim, or use Chinese characters in the pathname or file name used Modelsim, because Modelsim may not recognize Chinese characters and cause inexplicable errors.

3.3.2 Writing and compiling test files

Before writing testbench, it is best to compile the target file to be emulated into the working library, point Compile->compile or, the following dialog box will appear,

Figure 5 Compiling the target file

Select the working library in the library, find the target file to be emulated in the search scope (library Select the libraries you just created, look for the folder where the target file is located), then click Compile and Done, or enter vlog counter.v at the command line. The target file is now compiled into the work library, and the file will be discovered by expanding the work workspace in the library.

When simulation of the target file to be simulated, you need to provide the excitation source for each input variable in the file, and strict definition of the input waveform, this type of excitation source definition of the file is called Testbench, that is, test bench file. Let's talk about the method of producing testbench.

Method One: We can write the testbench directly within the Modelsim, and Modelsim also provides a variety of commonly used templates. The steps are as follows:

⑴ execute File->new->source->verilog, or simply click on the new icon on the toolbar, a Verilog document editing page will appear, in which the designer can edit the test bench file. It is necessary to note that many non-synthetic statements can be used here, and testbench is just an incentive source to produce files, as long as the input waveform definition and display some necessary information, remember not to make up too complex, so as not to distract.

⑵modelsim offers a lot of testbench templates that we can use directly to reduce our workload. In the blank space of the Verilog document editing page, right-click Show Language Templates then a load project will appear, and then you will find a Language Templates window on the left side of the document editing window, see.

Figure 6 Applying a template to generate a testbench file

Double-click creat testbench A Create wizard will appear, see.

Figure 7 Creating a wizard

Select the target file under the work workspace under the Specify Design unit workspace, click Next, and the following dialog box appears:

Figure 8 Setting up the Testbench Wizard

You can specify the name of the Testbench, the library to be compiled, and so on, where we use the default settings to directly point to finish. At this point in the Testbench will appear in the target file of the various port definitions and call functions next, the designer can add their own content to the Testbench (annotated for the added content), and then save in. v format. Follow the previous method to compile the Testbench file into the working library as well.

Figure 9 generated and modified Testbench files

Method Two: Write and compile testbench in Quartus II, then place testbench and target files under the same folder and follow the previous method to compile the Testbench and target files into the working library.

PS : If the file is not in the working library (in the case where the Testbench file does not have a port), the optimization option is removed in the Simulate-->start simulate card, as shown in. The file can be found in the working library after it is recompiled.

Figure 10 Removing the optimization option

3.3.3 Performing Simulations

Because the simulation is divided into pre-simulation and post-simulation, the following shows how to operate.

⑴ Pre-simulation

Pre-simulation, relatively simple. In the previous step we have compiled the required files into the working library, and now we just need to click Simulate->start Simulation or the shortcut button will appear in the Start Simulate dialog box. Click on the Design tab to select the Testbench file under work, then click OK, or you can double-click the Testbench file COUNTER_TB.V, the following interface appears.

Figure one start simulate

In the main interface will be more than a objects window, which shows all the signal pins defined in the Testbench, in the workspace will be more than a SIM tag. Right-click on COUNTER_TB.V and select Add->add to Wave as shown. Then the Wave window will appear and now it can be emulated, see.

Figure Wave Window

In the window has appeared to simulate the various signals, will start to perform simulation to 100ns, continue to point the simulation waveform also continues to extend, see.

Figure 13 Simulation Waveform

If the point is executed, the simulation continues until the point stops.

You can also enter commands at the command line: Run @1000

Simulation to 1000ns, the following 1000 can also be other values, the designer can modify. The next time the command is run, the current waveform continues to be emulated. At this point, the pre-simulation step is complete.

⑵ Post-simulation

Here is an example of the use of Cyclone II to do a counter.

Post-simulation is much the same as the previous steps, except that the simulation library (and all IP core-related), grid, and latency files need to be added in the middle of the process.

The premise of the post simulation is that Quartus has compiled the target file to be emulated, and generated the. vo file (Web table file) and. sdo file (latency file) required for the Modelsim simulation, and there are two ways to do it, one is to call Modelsim through Quartus, Quartus automatically adds the desired. vo file and the required emulation library to the Modelsim after compiling, which is easy to do by manually adding the required files and libraries to the Modelsim for simulation, which can increase the initiative Give full play to Modelsim's powerful simulation capabilities.

① calls through Quartus Modelsim

When you use this method, you first set the Quartus. Run the Quartus first, open the project to be emulated, click the assignments of the menu bar, point to the EDA Tool settings, select the simulation in the category on the left. Modelsim in the Tool name on the right ), select the following run Gate level Simulation automatically after complication. See.

Figure 14 Setting the Quartus

When the project in Quartus is ready, click the Start Complication button, and the Modelsim will start automatically, and Quartus is in the waiting state (provided that the path in the user variable in the system environment variable is set to the Modelsim installation path, such as: D:\ MODELTECH_6.3\WIN32). In the Open Modelsim Workspace window you will find more workspaces and libraries, and files in the work library that need to be emulated. Modelsim automatically compiles the quartus generated. vo file into the work library and builds the appropriate repository. is shown.

Figure Quartus II after compiling self-booting Modelsim

Observation Library, you can find that more Verilog_libs library, Gate_work Library and work library, but under "project folder \simulation\modelsim", only Verilog_libs and Gate_work folders, Why is there a work library in the library? and the Gate_work Library and work library file content is the same!

The Gate_work library is automatically generated after the Quartus II compilation, and the work library is the Modelsim default library. Careful observation of the two paths, both paths are the same, are Gate_work folder, it is known that Modelsim map Gate_work library to the work library. Therefore, the operation of Gate_work library or work library can get the correct result.

Write a test bench program COUNTER_TB.V, preferably in the same directory as the generated. vo file, to facilitate use when manual emulation is required. Click Compile to select the COUNTER_TB.V file in the dialog box that appears, then click the Compile button, and then click Done after compiling, and the test bench file will appear in the work library. As shown in.

Figure 16 Compiling the test file

Clicking the Simulate->start Simulation or shortcut button will appear in the Start Simulate dialog box. Click on the Design tab to select the COUNTER_TB.V file under work, then click the Libraries tab in the Search library and click the Add button to select the library for emulation (if you don't know which library to choose, You can go directly to the compile to see the name of the library that appears in the error prompt, and then repeat the steps above) see.

Figure 17 Selecting the library required for emulation

Click the SDF tab of the Start Simulate dialog box again. In the dialog box that appears, add the. SDO time-lapse file path within the SDF file box. In the Apply to box, there is a "/" in the front of the "/" to enter the test stand file name, that is "COUNTER_TB", after it is entered in the test bench program to call the test program when the name of the test program, in this case, "DUT", see. then click OK. The rear view waveform is the same as the previous simulation step.

Figure 18 Adding an. sdo file

The difference between automatic emulation and manual emulation:

This method is simpler because Quartus II calls Modelsim, so in addition to generating the. Vo Files (web table files) and. sdo files (latency files) that are required to automatically generate the Modelsim simulation, a gate_work folder, Verilog_ Libs folder, Gate_work folder (can be called the work Library, can also be called the compilation Library) to store the compiled files, verilog_libs folder for the simulation of the required library, the above example is the Cycloneii_ver Library (folder). Manual emulation requires you to add these files and libraries yourself. Specific as follows.

② manual emulation

Manual emulation requires you to add files and compile libraries yourself, but you can give full play to Modelsim's powerful simulation capabilities. The operation is also to set the Quartus first, set the same as the previous just do not select the run Gate level Simulation automatically after complication. Then start Modelsim and change the current path to "project folder \simulation\modelsim". As shown in.

Figure 19 Starting Modelsim

There are fewer libraries (actually verilog_libs libraries, gate_work libraries, and work libraries) than ①, so add a library below. Create a new library, where the default library name is work, at this time, the "project folder \simulation\modelsim" folder appears under the Works folder, there is no target files and test files under it, that is, there are no files in the The purpose of building a library is to put the compiled files in the library, which is placed under the folder. Before compiling, you also need to add the library cycloneii_atoms (used to EP2C8) required by the simulation, the cycloneii_ in the D:\altera\90\quartus\eda\sim_lib directory The atoms file is copied to the directory where. Vo is located, under "Project folder \simulation\modelsim".

If you write Testbench according to the method in ① and also in the same directory as the. Vo, the following dialog box appears in the compile or points below the point compile to compile the selected files.

Figure 20 compiling the required files and libraries

After the completion of the work, working in a lot of files, and also a lot more files (folders), the purpose of building a library is visible, including COUNTER_TB test files and counter target files. Clicking the Simulate->start Simulation or shortcut button will appear in the Start Simulate dialog box. There are only libraries tags in the search library when compared to ①, and the remaining 2 are the same. The libraries tag is set in the search library as.

Figure 21 Selecting the library required for emulation

The following observation waveform step is the same as the front face.

Iv. Some methods and techniques for observing waveforms. 4.1 Creating input waveforms manually (pending)

For complex design files, it is best to write your own testbench file, so that you can precisely define the various signals and the dependencies between each signal, and improve the simulation efficiency.

For some simple design files, the waveform window can also be used to create an input waveform for simulation. The specific method is to right-click the target simulation file COUNTER.V in the work library, then click Create Wave to pop the wave default window. As shown in.

Figure Add to Wave

In the Wave window, select the signal to create the waveform, in this case the CLK, then right-click, choose the Create/modify/wave entry appears in the following window:

Figure 23 Setting the input waveform

Select the type of input waveform in the patterns, then set the start time, end time and unit in the right window, then click Next to show the following window, we change the initial value of the Hiz to 0, then modify the clock period and duty cycle, then click Finish.

Figure 24 Setting the input waveform

Then continue to add other input waveforms, the following results appear. The red dots that appear earlier indicate that the waveform is editable. The following actions are the same as the methods used for testbench text emulation.

Figure 25 Simulation Waveform

4.2 Observing specific signal waveforms

If the designer only wants to see the waveform of the specified signal, you can select the signal to be observed in the Objects window, then right-click the add to wave->selected signals, and then add only the selected signal to the Wave window.

Figure 26 viewing specific signal waveforms

4.3 Saving and importing waveform files (pending)

If you want to save the current signal distribution in the waveform window, you can click File->save, set the save path and file name in the dialog box that appears, save the format as a. do file.

If you want to export the waveform you created (at the end of the article) you can choose File->export Waveform to select EVCD file in the dialog box that appears and make the relevant settings.

If the waveform of the imported design is selected File->import ECVD.

4.4 dataflow window to observe signal waveform

In the main interface point View->dataflow can see the dataflow window will appear, in the Objects window to drag a signal to the window, you will find in the dataflow window you just selected the signal is located in the module, if you double-click a pin of the module, Other modules or leads connected to the pin will appear, see.

Figure Dataflow Window

In the dataflow window View->show wave, a wave window appears in the Dataflow window, double-click a module in the window above, then in the Wave window below to show all the signals connected to the module, if the simulation has been performed, In the Wave window there will also be a corresponding waveform, see.

Figure Dataflow window to observe the simulation waveform

When you drag a cursor in the waveform window, the value of the pin signal of the above module changes as the cursor's current position changes.

If you want to modify the original design file in Modelsim, right click on the document page, cancel read only, you can modify, modify and continue the simulation. If you want to end the simulation to point Simulate->end Simulation, or enter Quit-sim directly on the command line, Quartus will also show the end of all compilation procedures.

v. Some notes

Questions about using ' timescale ' in Testbench

' Timescale is a compiler directive that defines the delay accuracy and delay units, and the command format is

' Timescale time_unit/time_precision

Where Time_unit defines the delay unit, which is the unit of delay value appearing in the later module, Time_precision defines the time delay accuracy. For example

The ' timescale 1NS/100PS indicates a delay unit of 1ns and a delay accuracy of 100PS.

If there are statements later #5. a=1;

The time-delay value of 5.22ns should correspond to 5.2ns, because the accuracy is 0.1ns.

If multiple modules in the design have their own ' timescale, the compile-time simulator is always defined on the minimum time-delay accuracy of all modules, and the delay in all modules is automatically converted to the minimum test precision.

Appendix:

Counter Source code:

' Timescale 1ns/100ps

Module Counter (

Input CLK,

Input Rst_n,

Output [3:0] CNT

);

reg [3:0] CNT;

Assign CNT = CNT;

[Email protected] (Posedge CLK, Negedge rst_n) begin

if (! Rst_n)

CNT <= #5 4 ' H0;

Else

CNT <= #0 cnt + 1 ' B1;

End

Endmodule

COUNTER_TB Source code:

' Timescale 1ns/100ps

Module COUNTER_TB;

Wire [3:0] CNT;

Reg Rst_n;

Reg CLK;

Counter

DUT (

. CNT (CNT),

. Rst_n (Rst_n),

. CLK (CLK));

Http://wenku.baidu.com/view/cd93f34ecf84b9d528ea7a95.html

Initial begin

#0 CLK = 1 ' b0;

Rst_n = 1 ' b0;

#5 rst_n = 1 ' B1;

End

50MHz

Always #10 CLK = ~CLK;

Endmodule

Thank you

Modelsim Primary Use Tutorial