Modulo-Number (A/d) converters

The basic principle of a/D conversion
The analog signals are sampled in a series of selected moments, then the sampled values are converted to the output digital quantities, and the conversion results are given in a certain encoding format.
The whole A/D conversion process can be divided into three processes: sampling, quantization and coding.
Second, sampling-holding circuit

Sample-hold the basic form of the circuit, for example, T is an n-channel reinforced MOS tube, used as a analog switch.

When the sampling control signal VI is high-normal t-conduction, the input signal VI is charged by the resistor R1 and T-capacitance ch. If the R1=RF is taken, and the apparent op amp is the ideal op amp, then after the charge is over, the VO=VCH=-VI

When VI returns to the low level, the MOS tube T cutoff, because the voltage on the CH in a period of time basically remains unchanged, so Vo also remains unchanged, the sampling results are preserved (the smaller the leakage current in CH, the higher the input impedance of the OP amp, the longer the VO remains).

The circuit in the sampling process requires the input voltage by R1 and T to capacitance CH charge, which limits the sampling speed, and by reducing the R1 method to improve the sampling speed will also reduce the circuit input impedance.

Third, parallel comparison type A/D converter

The circuit structure of the parallel comparator A/D converter is composed of a voltage comparator, a register and a code conversion circuit. The input is the analog voltage between the 0-vref and the output is a 3-bit binary digital d2d1d0.

　　

The way to quantify levels in a voltage comparator is to use a resistor chain to divide the reference voltage by Vref, to get (1/15) Vref to (3/15) Vref 7 comparison levels, which are quantified in (2/15) Vref, Compare these 7 comparison levels to the inputs of the 7 voltage comparator c1-c7, and simultaneously add the input analog voltage to the other input of each comparator, compared to the 7 baselines.

If vi< (1/15) Vref, all outputs of the comparator are all low, and all triggers in the register after the advent of the CLK rising Edge are set to 0 states

if (1/15) vref<vi< (3/15) Vref, only the C1 output is high, the CLK rising edge is reached after the FF1 is set 1, the rest of the trigger is placed 0

And so on, you can list the status of the register when VI is different voltage

The biggest advantage of the parallel comparator A/D converter is that the conversion speed is fast, and the time required for its one conversion only includes the flip time of the first level flip-flop and the transmission delay time of the three-stage gate circuit. However, from the circuit, the output is n-bit binary code converter should have (2^n)-1 voltage comparator and (2^n)-1 trigger, the scale of the circuit with the increase in the number of output code to expand sharply, the circuit more complex.

Iv. Feedback Comparison Type A/D converter

The feedback comparison type A/D converters are often used in both counting and successive asymptotic methods.

1, counting type

For example, the converter is composed of comparator C, D/A converter, counter, pulse source, control gate G and output register.

Step One: use the reset signal to zero the counter before conversion, and the conversion control signal should stay in the vl=0 state. At this time the gate G is blocked, the counter does not work. As the counter is added to the D/a converter is a full 0 digital signal, so vo=0.

Step Two: when the VL becomes high at the beginning of the conversion, pulses from the pulse through the gate G to the counter clock signal input CLK, the counter began to do the addition count.

Step three: as the count progresses, the analog voltage VO output of the D/a converter is also increasing. When VO increases to Vo=vi, vb=0, door g block, counter stop count. In this case the number stored in the counter is the desired output digital signal.

Because the number of counters in the conversion process changes constantly, so it is not appropriate to use the status of the counter as an output signal, set the output register at the output, after each conversion is completed, with the conversion control signal VL down the output of the counter to the output register, The status of the output register as the final output signal.

The disadvantage of this scheme is that the conversion time is too long, when the output is n-bit binary digital, the initial conversion time can be up to (2^n)-1 time times the clock signal period. The circuit of the scheme is relatively simple, and it is suitable for occasions where the conversion speed is not high.

2, successive progressive type

For example, the converter consists of 5 parts: Comparator C, D/A converter, register, clock pulse source, control logic, etc.

Step One: The register is cleared before conversion, so the amount of digital to D/A converter is also full 0;
Step Two: convert the control signal VL to high power start conversion, the clock signal first registers the highest position of 1, so that the output of the register is 100 ... 0;
Step Three: the output digital is converted to the corresponding analog voltage by the D/a converter and sent to the comparator and the input signal VI to compare. If Vo>vi, the figure is too large, then the 1 should be removed, if vo<vi, the figure is not large enough, this 1 should be retained;
Step four: follow the same method to the high position 1, and compare the size of VO and VI to determine whether the 1 of this bit should be retained, so that bitwise comparison down until the lowest bit comparison is complete. The digital stored in the register is the amount of digital that is being asked.
Successive asymptotic comparison of A/D converter is much faster than a count A/D converter, and in the output bit, the circuit scale is much smaller than the parallel comparison type, so the successive progressive A/D converter is currently the most used in the integrated A/D converter products.
Five-, two-integral A/D converters
For example, the converter includes integrator, comparator, counter, control logic, clock signal source and other parts

　　

Step one: Before the conversion starts (conversion control signal vl=0), the counter is cleared, and the switch is switched S0, so that the integral capacitor C completely discharged;

Step two: Make the switch S1 to the side of the input signal voltage VI, the integrator to the VI fixed time T1 integral, then

　　

Therefore, the digital quantity can be got:

　　

If you take T1 as an integer multiple of the TC,

　　

The advantage of the double-integral A/D converter is that the performance is stable and the anti-jamming ability is strong, but because it has carried out two times integral, its working speed is low, generally within dozens of times each time.

In addition, the conversion accuracy of the double-integral A/D converter is affected by several factors such as counter number, comparator sensitivity, op-amp, 0-point drift of the comparator, leakage of integral capacitance, instantaneous fluctuation of clock frequency and so on, so it is far from enough to increase the number of digits of conversion accuracy. In order to eliminate the 0-point drift of op-amp and comparator in practical circuit, a 0-point drift automatic compensation circuit is added, which can be used as a pulse source to prevent the frequency of clock signal from fluctuating during the conversion process.

Modulo-Number (A/d) converters