OpenGL design's tips

Simple FPGA design process:

 

1. Read the chip manual for use, mainly including the input and output port definition, design constraints, and example description;
2. Construct the circuit diagram and define the port of the design module based on the given requirements;
3. Use OpenGLCodeImplementation circuit;
4. Use testbench to test circuit function requirements.

 

Precautions In Design:

In the whole chip design project, encoding of behavior design and structure design is the most important step. It has an important impact on logical synthesis and wiring results, timing determination, verification capability, testing capability, and even product support. Considering the differences between the simulator and the real logic circuit, in order to effectively conduct the simulation test:

1. Avoid using internal clock
    The internal clock is called the gated clock ). If the external input clock and the door clock are both driven at the same time, the two steps are inevitably inconsistent, resulting in logical confusion. Moreover, the clock generated by the door will increase the difficulty of testing.And time.

 

2. Avoid using the asynchronous bit/reset signal generated internally.
    The preset/cleared signals generated internally may cause test problems, so that some output signals are set or cleared, and cannot be tested normally.

3. Avoid using latches
    Latches may cause test problems. Automatic Generation of test vectors (ATPG ),To enable scanning, the latches need to be set to the transparent mode. In turn, the test latches need to construct specific vectors, which can be unusual.

 

4. Clear Reset values must be set for the time series process.
    Enables the trigger to have a reset end. The entire circuit can be carried out during manufacturing testing, ATPG, and simulation initialization.   Fast reset.

5. Avoid the three-state/two-way mode in the module
    It is difficult to process internal three-state signals during manufacturing testing and logic synthesis. If the inout dual-port is used, another register should be referenced for caching.

Pay attention to the following during design:

1. The description of sensitive variables should be complete;
2. The condition description must be complete. For example, if the condition descriptions of the IF statement and case statement are incomplete, unnecessary latches may occur;
3. The left-side variable of the assign statement must be wire. When "=" is used to assign a value to a variable, the left-side variable must be reg;
4. Relationship between port I/O and Data Type:
Port I/O Port Data Type
Module Module external
Input Wire Wire or Reg
Output Wire or Reg Wire
Inout Wire Wire