PCIe Foundation (i) Operation configuration space

PCI Configuration Space

PCI has three address spaces: I/O space, memory address space, PCI configuration space. Bootloader at boot time
Or the kernel traverses the PCI bus and allocates resources such as interrupts and memory, and the device driver configures the space through the PCI
Locate the resource allocation. The size is 256 bytes.
To configure a spatial diagram:

(1) Device ID and Vendor ID register
The values of these two registers are assigned by PCISIG and are read-only. Where the vendor ID represents the manufacturer of the PCI device,
The device ID represents the specific equipment produced by the manufacturer. such as Intel's 82571EB chip-based
Serial network card with vendor ID 0x8086[1], and device ID 0x105e[2].
(2) Revision ID and Class code register
These two registers are read-only. Where the revision ID register records the version number of the PCI device. The register can be
is considered an extension of the device ID register.
(3) Header type Register
The register is read-only and consists of 8 bits. A 7th bit of 1 indicates that the current PCI device is a multifunction device and 0 is represented as
Single-function devices. The 6th to No. 0 bit represents the type of current configuration space, and 0 indicates that the device uses the PCI agent setting
Configuration space, common PCI devices use this configuration header, 1 for the configuration space using the PCI bridge,
The PCI bridge uses this configuration header, and for 2 represents the configuration space using the CardBus Bridge, the Card bus bridge uses
This configuration header is not interested in this type of configuration header. The system software needs to use this register to distinguish between different classes
PCI configuration space, the initialization of this register must correspond to the actual situation of the PCI device, and must be
A valid value.
(4) Subsystem ID and Subsystem Vendor ID Register
These two registers are similar to the device ID and the vendor ID, and are also the manufacturers and devices that record the PCI device
Name. However, these two registers and device IDs are slightly different from the vendor ID registers. Below with a
The instance describes the purpose of the Subsystem ID and subsystem Vendor ID. Xilinx Company in Fgpa
An IP core integrated with a PCIe bus interface, i.e. Logicore. Users can use Logicore to design each
PCIe Bus-based devices, but the device IDs of these devices are 0x10ee, and vendor
ID is 0x0007[3].
(6) Expansion ROM Base Address register
Some PCI devices need to complete basic initialization settings before the processor is running the operating system.
such as video cards, keyboards and hard drives and other devices. In order to achieve this "pre-implementation" function, the PCI device needs
A ROM program is provided, and the processor will run the ROM program during initialization to initialize the
Some PCI devices. The Expansion ROM base address records the base addresses of this ROM program.
(7) Capabilities Pointer Register
In PCI devices, this register is optional, but must be supported on Pci-x and PCIe devices
Capabilities Pointer Register holds the base address of the capabilities register set, the PCI
Use the Capabilities Register group to hold some extended configuration information related to PCI devices.
(8) Interrupt Line Register
This register is written when the system software configures the PCI device, which records the current PCI device
Using the interrupt vector number, the device driver can use this register to determine the current PCI device usage
Interrupt vector number in the manager system, and registers the driver's interrupt service routine with the operating system
[4]. The register is initialized by the system software and its stored value is associated with the 8259A interrupt controller, which
The value of the converter is also determined by the connection relationship between the PCI device and the 8259A interrupt controller. If you are in a processor
The system does not use the 8259A interrupt controller to manage interrupts for the PCI device, the data in the Register is
There is no point. In most PowerPC processor systems, the PCI setting is not managed using the 8259A interrupt Controller
Interrupt request, so the register is meaningless. Even in x86 processor systems, if I/O is used
The APIC interrupts the controller, and the contents of this register are still invalid. Currently, in the vast majority of processor systems,
This register is not used to hold the interrupt vector number used by the PCI device.
(9) Interrupt pin Register
This register holds the interrupt pin used by the PCI device, and the PCI bus provides four interrupt pin inta#,
intb#, intc# and intd#. A Interrupt pin Register of 1 indicates the use of the inta# pin to
The break controller submits an interrupt request, 2 means using intb#, 3 means using intc#, and 4 means that the
With intd#. If the PCI device has only one sub-device, the device can only use inta#;
A intb~d# signal can be used when a sub-device. If the PCI device does not use these interrupt pins, the
When the manager submits the interrupt request, the value of the register must be 0. It is worth noting that, while the PCIe device
Does not contain a inta~d# signal, but it can still be used because the PCIe device enables
Use INTX interrupt message to simulate the inta~d# signal of PCI device, see section 6th. 3.4.
Base Address Register 0~5 Register
This set of registers is referred to as the Bar register, and the bar register holds the base address of the address space used by the PCI device.
The base site holds the address of the device in the PCI bus domain. Each of these devices can have a maximum of 6
Base address space, but most devices do not use so many sets of addresses. After the PCI device is reset, the storage
The size of the base address space that the PCI device needs to use, whether the space is I/O space or memory space
[5], if the space is memory space can be pre-fetching, the system software to the PCI bus configuration, the first
Obtain initialization information in the bar register, and then write a reasonable base address based on the configuration of the processor system
into the corresponding bar register. The system software can also use this register to obtain the bar used by the PCI device
The length of the space, by writing 0xffff-ffff to the bar register and then reading the register.
When the processor accesses the bar space of the PCI device, it needs to use the base address provided by the Bar register. Worth noting
, the processor uses the address of the memory domain, and the bar register holds the address of the PCI bus domain. So at
The manager system does not directly access the register space of the PCI device using the "Bar Register + offset" method,
Instead, you need to convert the address of the PCI bus domain to the address of the memory domain. If the x86 processor system is enabled
After Iommu, these two addresses are not necessarily equal, so the processor system uses the PCI bus directly
The physical address of the domain does not ensure that access to the PCI device's bar space is correct. In addition to Linux
In the system, the input parameter of the IOREMAP function is the physical address of the memory domain and cannot be used
The physical address of the PCI bus domain. The address saved in the Pci_devàresource[bar].start parameter has been
Address translation through the PCI bus domain to the memory domain, so when writing device drivers for Linux systems,
You need to use the physical address in the Pci_devàresource[bar].start parameter and then go through the Ioremap
The function converts the physical address to the virtual address of the memory domain.
(one) command register
This register is the command register for the PCI device, which is initialized with a value of 0, at which time the PCI
The device cannot receive any memory or I/O requests other than to receive configuration request bus transactions. System
The device's memory or I/O space can be accessed after the register is properly set up. In
On a Linux system, the device driver calls the Pci_enable_device function to enable the I/O of the Register and
Memory space to access the device's storage or I/O address spaces.
() Status Register
Most bits of the register are read-only, saving the state of the PCI device.

PCIe Foundation (i) Operation configuration space