Preemption priority, response priority concept in STM32

There are two priority concepts in STM32 (CORTEX-M3)-preemptive priority and response priority, where the response priority is referred to as ' sub-priority ' or ' secondary priority ', and each interrupt source needs to be assigned two priority levels.

Interrupts with a high preemption priority can be responded to during interrupt processing with low preemption priority, that is, interrupt nesting, or that high preemptive priority interrupts can be nested in a low preemption priority interrupt.

When the preemption priority of the two interrupt sources is the same, the two interrupts will not have a nested relationship, and when an interrupt arrives, if another interrupt is being processed, the subsequent interrupt is processed until the previous interrupt has been processed. If both interrupts arrive at the same time, the interrupt controller decides which one to process first based on their response priority, and if their preemption priority and response priority are equal, whichever is processed first based on the order in which they are ranked in the interrupt table.

After reading the above introduction, I believe we all understand the relationship in this, summed up is: Preemptive priority > Response Priority > Interrupt table in the row order (where ">" is understood as the direction of the comparison).

It is precisely because each interrupt source needs to be assigned these two priority levels, it is necessary to have the corresponding register bit to record each interrupt priority, in CORTEX-M3 defined 8 bits to set the priority of the interrupt source, these 8 bits can have 8 kinds of allocation, as follows:

1. All 8-bit to specify response priority

2. Up to 1 bits to specify preemption priority, minimum 7 bits to specify response priority

3. Up to 2 bits to specify preemption priority, minimum 6 bits to specify response priority

4. Up to 3 bits to specify preemption priority, minimum 5 bits to specify response priority

5. Up to 4 bits to specify preemption priority, minimum 4 bits to specify response priority

6. Up to 5 bits to specify preemption priority, minimum 3 bits to specify response priority

7. Up to 6 bits to specify preemption priority, minimum 2 bits to specify response priority

8. Up to 7 bits to specify preemption priority, minimum 1 bits to specify response priority

The above is the concept of priority grouping, but CORTEX-M3 allows a smaller number of register bits to be used to specify the priority of the interrupt source with fewer interrupt sources, so STM32 reduces the register bit for the specified interrupt priority to 4 bits, and the 4 register bits are grouped as follows:

Group No. 0: All 4 bits are used to specify the response priority

Group 1th: Up to 1 bits to specify preemption priority, minimum 3 bits to specify response priority

Group 2nd: Up to 2 bits to specify preemption priority, minimum 2 bits to specify response priority

Group 3rd: Up to 3 bits to specify preemption priority, minimum 1 bits to specify response priority

Group 4th: All 4 bits are used to specify preemption priority

Here are the--nvic_prioritygroupconfig (u32 nvic_prioritygroup) for the relevant functions in the firmware library mentioned in the first article, and there are 5 parameters for the function:

The parameter of this function (Nvic_prioritygroup value) has the following 5 kinds:

Nvic_prioritygroup_0 = Select the No. 0 Group//is all the response priority, all interrupts can not preempt other interrupts.

nvic_prioritygroup_1 = Select 1th Group//Two preemption priority

nvic_prioritygroup_2 = Select 2nd Group//4 preemption Priority

nvic_prioritygroup_3 = Select 3rd Group//8 preemption Priority

nvic_prioritygroup_4 = Select 4th Group//16 preemption Priority, no response priority. When all interrupts arrive, other priority interrupts can be preempted at the priority level.

This is also very good understanding, such as the choice of nvic_prioritygroup_1, then preemptive priority is a bit, that is, there can be 2^1 levels, can be set to 0 and 1, and the response priority is 3 bits, that is, you can have 2^3 choices, can be set to 0~ 7; In total, you can distinguish between the >16 priority (why it is greater than, but not equal to, think should be understood)

For example, if there are 4 external interrupts, and there is a exti9_5 interrupt, then if the priority group is selected as group 1th, then there are only two preemption priorities, 5 interrupts at least 3 are the same priority on preemption priority, and the other two are at the priority level. Then there are 8 options for setting the response priority, and if there are now two preemptive-priority interrupts at the same time, then the order of the processing is who has the highest priority, and the other is the one that needs attention, If you enter this interrupt and then come up with a preemptive priority but a higher-priority interrupt, this will not interrupt an existing interrupt.

Preemption priority, response priority concept in STM32