PXA270 embedded system design (2)-clock and reset

Author:Liu Hongtao, senior lecturer of Huaqing vision embedded College, and an arm ATC authorized training instructor.

Recently, I plan to develop a PXA270 system for our far-sighted teaching in Huaqing. I will record some of my software and hardware development processes and share and discuss them with you. Have good suggestions everyone must communicate in time, lht@farsight.com.cn. In the previous article, I wrote "PXA270 embedded system design 1: Power Supply Management". Today, I want to write about the clock and reset. Thank you for your attention ~~

I. Clock part

Any processor requires at least one clock source. There will be corresponding clock management units in the processor to provide a proper clock for the CPU and various functional control units.

The PXA270 processor requires two external oscillator, one 13 m and one 32.768 K. Their respective functions:

• The 13 m clock is mainly used to generate the reference clock for each PLL of the system. It can also provide the clock for some low-speed controllers;
• The 32.768k clock is mainly used to provide a real-time clock source for the RTC controller, or for some low-speed controllers.

The PXA270 processor has two internal PLL units, one being the peripheral PLL and the other being the core PLL.

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• After the peripheral PLL is enabled, a fixed M clock is generated, which is used to provide the clock source for the high-speed controller;
• The core PLL can generate a 26-624m clock for CPU, memory controller, system bus, and LCD controller.

The circuit diagram of the clock part:

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Ii. Reset part

PXA270 provides five reset methods:

• Power-On Reset: When the vcc_batt pin is powered on for the first time, it is a full reset.
• Hardware reset: it is also a full reset that is generated when the nreset pin is set.
• Watchdog Reset: triggered by the watchdog controller. It is a partial reset. For details, see the PXA270 chip manual.
• Gpio Reset: a form of hardware reset that can be triggered by external signals. It is also a full reset.
• Sleep exit Reset: reset the modules that are powered off during sleep and deep sleep.

Circuit schematic diagram related to reset in the system.

• Power-On Reset

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• Hardware reset

Is the connection between max1586c and the system reset circuit.

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K1 is the reset button, and the nrso signal is output through the reset management circuit of max1586c. If the system does not have a reset management circuit similar to max1586c, you can use a reset chip similar to max811 to complete the reset, you can also use the resistance and some logical circuits to complete the reset.

Note: The Mr pin reset of max1586c resets the V3 output of max1586c to 1.3 V, without affecting other voltage outputs.

Is the connection between the reset signal and the nreset of PXA270.

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When nreset is set or the watchdog controller is reset, nreset_o can both be set. You can use it to reset other peripheral chips.

It is a JTAG circuit, and its reset signal must be connected to the system's nreset.

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The clock reset section is roughly so much.