Quickly view pre-simulation waveforms with Debussy+modelsim

Introduction: Modelsim is the HDL simulation software, Debussy is the waveform viewing software, with the use, quite cool. Here the so-called rapid view before the simulation waveform is only a point, we do not adhere to this. Two software features are very powerful, please do your own research.

Note: The software environment for this blog post is: Debussy 5.3v9 + Modelsim SE 6.5

Configuration Chapter

1 installation, Harmony Software. Slightly.

2 Copy file: \novas\debussy\share\pli\modelsim_pli\winnt\novas.dll to folder: \modeltech_6.5\win32.

3 Cancel File: after the read-only property is \modeltech_6.5\modelsim.ini, open.

Found it

1	; Veriuser = veriuser.sl

Replaced by

1	Veriuser = novas.dll

Save, close, set to read only.

After the configuration, once and for all.

Real-Combat Chapter

Here is an example of a simple divider. The file map is as follows:

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│  rtl.f│  run.bat│  sim.do│  └─rtl        clk_rst.v        divider.v        divider_tb.v

1 Write the HDL file you want to simulate: RTL-level Code +testbench code. Save in the folder RTL .

(1) DIVIDER.V//RTL-Level code module

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`timescale1ns/10psmoduledivider(  inputi_clk,  inputi_rst_n,     outputo_clk); parameterU_DLY = 1;// log2(5) = 2.3219 <= 3  reg[2:0] cnt_p;                        // 上升沿计数子 // 5位上升沿计数器: 0 ~ 4// 4 = 5 - 1always@ (posedgei_clk, negedgei_rst_n)begin  if(!i_rst_n)    cnt_p <= 0;  else    begin    if(cnt_p == 4)      cnt_p <= 0;    else      cnt_p <= #U_DLY cnt_p + 1‘b1;    endend // log2(5) = 2.3219 <= 3  reg[2:0] cnt_n;                        // 下降沿计数子// 5位下降沿计数器: 0 ~ 4// 4 = 5 - 1always@ (negedgei_clk, negedgei_rst_n)begin  if(!i_rst_n)    cnt_n <= 0;  else  begin    if(cnt_n == 4)      cnt_n <= 0;    else      cnt_n <= #U_DLY cnt_n + 1‘b1;  endend rego_clk_p;                            // 上升沿时钟输出寄存器// 输出上升沿时钟// 0     ~ 2 ↑-> 1// (2+1) ~ 4 ↑-> 0// 2 = 5>>1// 4 = 5 - 1always@ (posedgei_clk, negedgei_rst_n)begin  if(!i_rst_n)    o_clk_p <= 0;  else  begin    if(cnt_p <= 2)                     // 2 = 5>>1      o_clk_p <= 1;    else      o_clk_p <= 0;  endend rego_clk_n;                            // 下降沿时钟输出寄存器// 输出下降沿时钟// 0     ~ 2 ↓-> 1// (2+1) ~ 4 ↓-> 0// 2 = 5>>1// 4 = 5 - 1always@ (negedgei_clk, negedgei_rst_n)begin  if(!i_rst_n)    o_clk_n <= 0;  else  begin    if (cnt_n <= 2)                     // 2 = 5>>1      o_clk_n <= 1;    else      o_clk_n <= 0;  endendassigno_clk = o_clk_n & o_clk_p;       // 按位与(作用:掩码) endmodule

(2) CLK_RST.V//Testbench clock and Reset module

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`timescale1ns/10psmoduleclk_rst(  outputregi_clk,  output regi_rst_n);parameterCLK_PERIOD = 20;parameterMULT_RATIO = 10;parameterRESET_TIME = MULT_RATIO * CLK_PERIOD + 1;initialbegin  i_rst_n <= 1‘b0;  #RESET_TIME i_rst_n <= 1‘b1;endinitialbegin  i_clk <= 1‘b0;  forever    #(CLK_PERIOD / 2) i_clk <= ~i_clk;endendmodule

The clock and reset are stripped separately to facilitate porting to other platforms.

(3) DIVIDER_TB.V//testbench Top-level case module

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`timescale1ns/10psmoduledivider_tb();wirei_clk;wirei_rst_n;wireo_clk;// genrate clockclk_rst clk_rst_inst(  .i_clk(i_clk),  .i_rst_n(i_rst_n));// user logicdivider divider_inst(  .i_clk(i_clk),  .i_rst_n(i_rst_n),  .o_clk(o_clk));// dump fsdb file for debussyinitialbegin  $fsdbDumpfile("wave.fsdb");  $fsdbDumpvars;endendmodule

Note Lines 22nd through 27th

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// dump fsdb file for debussyinitialbegin  $fsdbDumpfile("wave.fsdb");  $fsdbDumpvars;end

The meaning of this statement is to call Modelsim to generate the waveform file and save it as Wave.fsdb for Debussy viewing.

2 Write the HDL file list file for Modelsim and Debussy use.

Rtl.f

123	rtl/divider.vrtl/clk_rst.vrtl/divider_tb.v

3 Write the Modelsim command line script file.

Sim.do

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vlib workvlog -f rtl.fvsim work.divider_tbrun 10usq

4 Write Batch footstep file, call command line Modelsim generate waveform file, then call Debusyy view.

Run.bat

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::关闭回显@ECHO OFF::设置软件路径SET debussy=C:\Novas\Debussy\bin\Debussy.exeSET vsim=C:\modeltech_6.5\win32\vsim.exe::ModelSim Command%vsim% -c -do sim.do::删除ModelSim生成的相关文件RD work /s /qDEL transcript vsim.wlf /q::Debussy Command%debussy% -f rtl.f -ssf wave.fsdb -2001::删除波形文件DEL wave.fsdb /q::删除Debussy生成的相关文件RD Debussy.exeLog  /s /qDEL debussy.rc /q::退出命令行EXIT

Note: Please modify the relevant path as appropriate, just take my personal configuration as an example.

5 Double-click Run Run.bat

Show Command line screen

Figure 1 Running the Run.bat screen

Pop-up Debussy and Debussy waveform viewing components.

Figure 2 Debussy and Debussy waveform viewing components

I call, where is the waveform. How dare you bluff me.

Oh, don't worry, slow down.

(6) Add to watch the signal.

Click or Signal-get signals ... Add a signal, or be lazy, click Signal-get all signals. Here I am lazy to the end, just add all the signals it.

A pop-up warning tells us that adding all the signals takes a while to confirm. Confirm OK.

Figure 3 Warning

Look, the waveform came out.

Figure 4 Devider Pre-simulation waveform

Conclusion

As the introduction says, Modelsim's function is too powerful, so it's a bit cumbersome. and Debussy Collaborative simulation, we save a lot of unnecessary, why not. Of course, there are a lot of features, because the level is limited, it is written here.

Quickly view pre-simulation waveforms with Debussy+modelsim