Re-learning STM32---(iii) Interrupt grouping and prioritization

See the majority of days, finally the atomic brother in the example of the interrupt group and priority to understand, barely know how to set the interrupt grouping and priority,, not easy ah. Here's the information I've collected and my understanding.

Grouping is not difficult, there is a little to know it all understand:

Set Nvic grouping

Nvic_group:nvic Group 0~4 Total 5 groups

void My_nvic_prioritygroupconfig (U8 nvic_group)

{

U32 TEMP,TEMP1;

temp1= (~nvic_group) &0x07;//after three digit see after note

temp1<<=8; Because priority is grouped in 8-10-bit

temp=scb->aircr; Read the previous settings

temp&=0x0000f8ff; Empty previous groupings

temp|=0x05fa0000; Write key look register

TEMP|=TEMP1;

scb->aircr=temp; Set grouping

}

temp1= (~nvic_group) &0x07;//take three bits why nvic_group to take the reverse? Isn't the CM3 group reversed? A closer look at the CM3 authoritative guide and the comparison of the STM32 incomplete handbook reveals that STM32 is the No. 0 group that defines the 7th grouping in the CM3 kernel as STM32! Atomic brother aside STM library function to write their own, actually write is the kernel driver, so now we want to control is not STM32, but CM3, in order to and STM32 document correspondence, then we should nvic_group take the reverse! For example, I now want to use the STM32 in the 1th group, in fact, CM3 in the 6th group, then I should be 0x600 write into cm3!

Set Nvic

Nvic_preemptionpriority: preemption Priority

Nvic_subpriority: Response Priority

Nvic_channel: Interrupt Number

Nvic_group: Interrupt Grouping 0~4

Note that the priority cannot exceed the range of the set! Otherwise there will be unexpected errors.

Group Division:

Group 0:0-bit preemption priority, 4-bit response priority

Group 1:1-bit preemption priority, 3-bit response priority

Group 2:2-bit preemption priority, 2-bit response priority

Group 3:3-bit preemption priority, 1-bit response priority

Group 4:4-bit preemption priority, 0-bit response priority

The principle of nvic_subpriority and nvic_preemptionpriority is that the smaller the number, the higher the priority

void My_nvic_init (U8 nvic_preemptionpriority,u8 nvic_subpriority,u8 nvic_channel,u8 nvic_group)

{

U32 temp;

My_nvic_prioritygroupconfig (Nvic_group);//Set grouping (see above analysis)

temp=nvic_preemptionpriority<< (4-nvic_group); //The bit4-7 is set to priority.

And the priority setting is determined by the grouping

0-Group: 0-bit preemption priority, 4-bit response priority (BIT4-7)

1-Group: 1-bit preemption priority (BIT7), 3-bit response-first (bit4-6) level

2-Group: 2-bit preemption priority (BIT6-7), 2-bit response priority (BIT4-5)

。。。。 So here we subtract nvic_group.

temp|=nvic_subpriority& (0x0f>>nvic_group);

temp&=0xf; Take four-bit lower

Nvic->iser[nvic_channel/32]|= (1<<NVIC_CHANNEL%32); Stm32 as many as 200 interrupts, do not remember, NVIC_CHANNL representative of one, such as USART2_IRQN = 38. These interrupts are enabled by 8 32-bit registers, take USART2_IRQN, 38/32 =1,38%32=6, so to make the USART2 interrupt enabled, the nvic->iser[1] sixth bit must be set to 1 (see Register below)

nvic->ip[nvic_channel]|=temp<<4; Set response priority and steals priority

}

Insert a Nvic register again, (in the M3 authoritative guide):

Re-learning STM32---(iii) Interrupt grouping and prioritization