Reading the audio/video decoding module

1. initialize the platform before decoding audio and video:
Initplatform (){
...
}
This function mainly completes the following tasks:
First, clear the system control information and video buffer information.
Hi_mpi_sys_exit ()
Hi_mpi_vb_exit ()

Next, set the video buffer.
First configure the size of several video Buffers
Stvbconf. astcommpool [0]. u32blksize = 720*576*2;/* D1 */
Stvbconf. astcommpool [0]. u32blkcnt = 10;
Stvbconf. astcommpool [1]. u32blksize = 704*576*2;/* D1 */
Stvbconf. astcommpool [1]. u32blkcnt = 52;
Stvbconf. astcommpool [2]. u32blksize = 384*576*2;/* 2cif */
Stvbconf. astcommpool [2]. u32blkcnt = 64;
Stvbconf. astcommpool [3]. u32blksize = 384*288*2;/* CIF */
Stvbconf. astcommpool [3]. u32blkcnt = 20;

Set the number of bytes alignment of the image in the system. We recommend that you set it to 16 or 64 in the development documentation.
Stsysconf. u32alignwidth = 64;
Hi_mpi_vb_setconf (& stvbconf );
Video buffer Initialization
Hi_mpi_vb_init

2. Complete the initialization of the system platform, and then perform audio and video input.
In video input processing, there must be a clear concept: the VI device port, hi3520 has four VI device ports, and a maximum of 16 ch video input is supported.
That is to say, one VI device port corresponds to four video input ports.
Video Input initialization must complete the following work.
Set the port attribute hi_mpi_vi_setpubattr of the VI device.
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V
VI device enabling hi_mpi_vi_enable (videv)
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Set the properties of the VI device port to access each VI Channel

In hi3520 system, data outside the 3520 chip is stored in the memory area outside the chip through the ITU-R bt656/601/1120 interface or digital camera interface,
When the data interface is itu_r bt656, a VI device can support multiple channels and a maximum of four channels are supported. We call it vichn0, vichn1, vichn2, and vichn3.

1. Set VI device port Properties
Set the property interface function. vi_dev videvid VI inputs the device port and pstpubattr sets the property value.
Hi_s32 hi_mpi_vi_setpubattr (vi_dev videvid, const vi_pub_attr_s * pstpubattr );

Typedef struct hivi_pub_attr_s
{
Vi_input_mode_e eninputmode;/* video input mode */

Vi_work_mode_e enworkmode;/* Work mode (only for bt.601 )*/
Video_norm_e envinorm;/* Video Input normal (only for bt.601 )*/
Hi_bool bischromachn;/* Whether this device capture chroma data (only for bt.1120 )*/
Hi_bool bchromaswap;/* Whether exchange U/V of chroma channel (only for bt.1120 )*/
} Vi_pub_attr_s;

Hi_mpi_vi_enable (videv );

2. After setting the video input device, set the video input channel.
A video input device corresponds to four channels.
Set channel properties just like video input device settings
S32ret = hi_mpi_vi_setchnattr (videv, vichn, pstvichnattr );
Next, enable the channel
S32ret = hi_mpi_vi_enablechn (videv, vichn );
Set the number of frames per second for the channel. The value is 30 in N and 25 in palth.
S32ret = hi_mpi_vi_setsrcframerate (videv, vichn, u32srcfrmrate );

The entire process of video decoding should at least know how data is collected.
Step 1: analog signal acquisition
The analog signal is collected by a 2866 chip and converted to a digital signal. The 2866 chip is a standard ad and DA data conversion chip. In our system, we mainly implement analog signal to digital signal input, and digital signal to analog signal output.
Up to 2866 video signals can be collected simultaneously.
Step 2: modulus Conversion
The 4ch video signal collected by 2866 (analog) is converted into a 1ch digital signal and sent to the 3520 chip. For a newbie like myself, it may be difficult to understand here, Why 4 ch analog signal

The input 2866 is only a 1ch digital signal. This involves the knowledge of a little bit of electricity. A digital signal is a high level, a high level represents 1, a low level represents 0, and a 1 Ch Digital Signal

Which of the following is a 4-way VI video? Assume that the video digital signal sent from 2866 is a waveform in a clock cycle,

-_--_-_--__---_--_-_--__---_--_-_--__----_--_-_--__----_--_ -_--__-----_-

The first four signals of the cycle-_ -- the first video signal whose signal value is vi1, the second video signal whose signal value is vi2, and the third video signal whose signal value is vi3, the fourth signal is worth the vi4 video signal.
Step 3: 2866 output video data to 3520
In this case, a concept is introduced: VI device, what is a VI device. For 3520, the one-channel video signal after the 4 ch analog signal is converted from the previous step 2866 is a VI device, the VI device simultaneously processes 4 channels of video data.
The main task of the hith VI module is to process the 4ch video data of the VI device and put the video data into the memory area. In the future, the memory data will be used for video output or video encoding.

 

Refer:

1. Reading Notes of the audio/video decoding module (1) --> reprint

Http://blog.csdn.net/u012236632/article/details/43015233

Reading the audio/video decoding module