Register, the circuit principle of the shift register and the Verilog code implementation

Register: A circuit for storing binary code, a 4-bit digital register consisting of a Wirtgen block D trigger:

Logic function Analysis:

1. Asynchronous side CR 0 o'clock, output 0;

2. Synchronous parallel Position: D0~D3 is 4 input code, when the CP Rising Edge arrives, D0~d3 is simultaneously placed in parallel.

3. At the end of the 1,CP, the end is 0 o'clock and remains unchanged.

2. Shift register: A circuit that holds digital and makes the digital shift right or left is called a shift register.

Shift registers can be divided into different types according to different classification methods. If classification according to shift direction of shift register, it can be divided into left shift shift register, shift register and bidirectional shift register, etc., if classified according to the mode of operation, it can be divided into serial/serial shift register, serial in/out shift register and merge/String out shift register, etc.

The following is an asynchronous zeroing 4-bit merge sequence shift register (input as parallel data, output as serial data)

ModuleREG_BC (clk,clr,din,dout);inputCLK,CLR;//input clock End, clear 0 end (active high)input[3:0] DIN;//Data-EntryOutputDout//Data Output EndReg[1:0] CNT; Reg[3:0] Q;Regdout; always@(PosedgeClk//clock rising edge triggerbeginCNT<=cnt+1;//CNT Self-add 1if(CLR)//determine if clear 0 signal is validbeginQ<=4'b0000;//q 0EndElsebeginif(cnt>0)//determine if CNT is greater than 0beginq[3:1]<=q[2:0];//the value in Q moves 1 bits to the leftEndElse if(cnt==2'b00)//Determine if CNT is 0beginQ<=din;//Give the value of DIN to QEnddout<=q[3];//put the highest bit of Q outEndEnd

Register, the circuit principle of the shift register and the Verilog code implementation