Single-chip computer interrupt IE and IP register (excerpt)

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One InterruptsAllow registers IE
The CPU's control of the interrupt source's open or interrupt masking is set by the interrupt allow register IE, which can be addressed by byte address (its byte address is a8h) and bitwise addressable. At89s52 Single Chip microcomputerThe 6 interrupt vectors are masked interrupts, which allow or prohibit an interrupt by certain position and clear 0 of IE, and block all interrupt sources when the EA bit of IE is cleared 0 o'clock. The function of each flag bit in IE is shown in table 1:

Example: Open External interrupt 0
byte operation: mov IE, #81H or mov 0a8h, #81H
Bit operation: Setb EA SETB EX0
Second, the AT89S52 priority register IP
The interrupt system of the AT89S52 microcontroller provides two interrupt priority, which can be programmed as a high-priority interrupt source or a low-priority interrupt source for each medium-fault request source to achieve level two interrupt nesting. Interrupt priority is controlled by the on-chip interrupt priority register IP (special function register). IP Register byte address bit b8h, can be bit addressable. The functions of the IP flag bits are shown in table 2:

The AT89S52 interrupt system has a level two priority (the priority of each interrupt source is divided into high and low priority by the IP register), and they follow the following two basic rules:
(1) A low-priority interrupt source can be interrupted by a high-priority interrupt source, and a high-priority interrupt source cannot be interrupted by any interrupt source;
(2) An interrupt source (whether high priority or low priority), once it is responded to, can no longer interrupt the source of its peers.
To implement the two rules above, the interrupt system contains two non-addressable priority state triggers. One is used to indicate that a high-priority interrupt source is receiving the service and to block all other interrupts, while the other triggers that a low-priority interrupt source is being serviced and all sibling interrupts are blocked, but the high-priority interrupt source is not blocked. When you receive several interrupts of the same priority at the same time, the response to which interrupt source depends on the internal query order. The priority arrangement is shown in table 3.

Single-chip computer interrupt IE and IP register (excerpt)