Soc Embedded Software Architecture Design II: No MMU design and implementation of CPU virtual memory management

Most of the program code is necessary when it can be loaded into memory to run. After surgery, you can discard or overwrite other code directly. Our PC at the same time a large number of applications, able to the entire linear address space (in addition to the part of the operating system or reserved for it), can feel that each application is exclusive of the entire virtual address space (Word is 32 CPU is 4G virtual address space), but our physical memory is only 1G or 2G. That is, multiple applications compete to use this physical memory at the same time. It is bound to cause a certain fragment of the program to run at some point, that is, all program code and data time-sharing physical memory space -This is the Memory Management Unit (MMU) work core role.

Processor family of chips (such as X86, ARM7 or more, MIPS) will generally have MMU, with the operating system to achieve virtual memory management, MMU is the Linux, wince and other operating system hardware requirements. and the controller system chip (for low-end control field, arm1,2. MIPS M Series. 80251, etc.) generally there is no MMU, or it has only a single linear mapping mechanism.

This paper is about the hardware design of the memory management unit of the controller Domain Soc. The important concept is the same as code and data time-sharing physical memory space, in order to ensure the system functions and performance based on the maximum savings of physical memory.

Related articles include: one of theSoc software Architecture design: System memory requirements Assessment and memory-saving software design techniques .

I. Working mechanism of the Memory Management Unit (MMU)

Before describing the memory management in the controller domain, we should first introduce the virtual memory management mechanism in the processor domain, the former is a reference to the core mechanism of the latter largely. There are several modules for implementing virtual memory Management: CPU, MMU, operating system, physical memory, as shown (if there is no cache for this chip series):

We analyze the process of CPU access to memory, if addressing is 0x10000008. A page size of 4K (12 bits). The virtual address is divided into two parts: the page Map section (20bit,0x10000) + The In-page offset (12bit, 0x8). The CPU sends the address signal (0X10000008) via the bus to Mmu,mmu to match the page map portion of the address (20bit) to the TLB.

What is a TLB? Translation Lookaside Buffer. Online there is called "Translation backup buffer".

This translator does not know what it is doing.

Its role is to buffer the page table. I like to call it a page table cache.

The structure of the diagram is as follows:

As you can imagine, a TLB is an array of indexed addresses, and each element of an array is an index structure, including the virtual page address and the physical page address.

It behaves as a register form inside the chip. The general register is 32 bits, and the page address in the TLB is actually a 32-bit register. Just the index comparison is compared to the first 20bit, after 12bit is actually practical. For example, being able to set a bit is a permanent representation. That is, the index is always valid and cannot be replaced, and such scenarios are often designed to accommodate some of the most demanding performance-specific codec algorithms. A memory-resident is typically replaced at some point, such as when a TLB fills up with a new page address.

1) if the first 20bit of 0x10000008 is hit in the first M index of the TLB. This means that the virtual page has allocated the appropriate physical memory to it in physical memory. The page table is also well documented. As for the virtual address, the corresponding code page is stored from the outside (Flash. Card, hard disk) in the program to load into memory also need to have additional tags, how to mark it? is to use the above mentioned TLB low 12 bits of a bit (which we call K) to identify, 1 identification code data has been loaded into memory, 0 means not yet loaded into memory.

If it is 1, it will use the physical address in M as high 20bit, the page offset 0x8 as low as 12bit. form a physical address and send it to memory to access it. The interview will be completed at this time.

2) if k is 0, that means that the code data has not yet been loaded into memory. The MMU then outputs the signal to the interrupt management module. Triggering an interrupt for the kernel State is the responsibility of the operating system to load the corresponding code page into memory. and change the K-bit and TLB corresponding entries of the corresponding page table entry K-bit is 1.

3) If the first 20bit of 0x10000008 does not have a hit in all of the TLB's indexes. The MMU will also output a signal-triggering interrupt into the kernel state to the Interrupt management module. By the operating system to move the 0x10000008 right 12 bits (that is, divided by 4K) to the page table to obtain the corresponding physical page value, if the physical page value is not 0 valid, the code is loaded into memory, then the page table entry value into one of the spare TLB entries. If the physical page value is 0, indicating that the virtual page has not been allocated the actual physical memory space, then it will be assigned to the actual physical memory, and write good page table of the corresponding item (k is 0), and finally write this index entry in one of the TLB.

2) and 3) are in fact broken down in the kernel state, why not a piece of it? The main reason is that one interrupt should not do too much. To increase interrupt latency. Affect system performance. Of course, it is understandable to assume that a chip will make an interruption. Let's take a look at the structure of the page table.

Page tables can of course be indexed as TLB, but there are two bad places:

1) the page table is to map all the virtual pages. Its maintenance in memory also requires a small amount of space. When the page size is 4K, all that is mapped is the 4g/4k=1m index, with each index 4*2=8 bytes, which is 8 m of memory.

2) If you press the TLB structure. The process of matching the index is a for loop matching circuit, the efficiency is very low, you know we do this is in the interrupt state is complete.

So the General page table is designed as a one-dimensional array. That is, the entire linear virtual address space is the index of the array in the order of the page. That is, the first word (4 bytes) of the page table maps the minimum 4 K of the virtual address space. The second word maps the second 4K with the lowest virtual address, and so on, the nth word of the page table maps the nth 4K space of the virtual address space. That is (N-1) the address space of the *4k~4kn. So the size of the page table is 1m*4=4m bytes, and when the index is matched is only an offset calculation, very soon.

Two concepts are understood before the second part is drawn up:

1. Bank represents the meaning of the code chunking, similar to the concept of the page mentioned above.

2. Different code time-sharing memory: Different code means different virtual address corresponding code, (the program is linked to the address is a virtual address), memory is physical memory. The code for different virtual addresses of a certain size runs in a certain amount of physical memory space at different times. Each block of code is a different code bank.

Second, the controller domain SOC memory management Unit hardware design

This refers specifically to the SOC design without a memory management unit, typically to reduce costs when performance is sufficient. Assuming that the 16-bit or 24-bit word-length CPU solves this problem, it is generally not possible to choose a 32-bit-word CPU, unless it is a computational performance consideration, or the license of a 32-bit CPU is cheaper (typically very rare). It is only possible to achieve efficient memory management to achieve the purpose of physical memory time-sharing, which can be called success or effective. Before introducing a real memory management unit hardware design, let's introduce a mechanism for using tool chains to implement memory time-sharing. Then combined with the MMU and this tool chain implementation of the block processing method to design our new memory management unit, including its hardware working mechanism and software design and key mechanisms.

Because the following content involves in the trial patent, after consideration, temporarily hide the following content, in due time again public. I'm sorry.

xxxxxxx

PostScript Supplement

When integrating a CPU without the MMU, the SOC implements memory management and requires an additional memory management module. Implement the core function of the MMU, which is the function of code paging (block) mapping. and need to simplify the design to achieve the highest efficiency, at the same time the code block needs to be directly on the link script now. In pursuit of efficiency, the executable file compiled after linking is also organized into a more streamlined run file by offline parsing. Delete all unnecessary segments and put the block code in a logical order. To facilitate faster loading of the system when necessary.

Of course. The operating system's code memory management also needs to be in line with the memory management hardware circuitry and can parse the running Program files once again packaged. Therefore, the implementation of memory management requires the architect to consider the software and hardware comprehensively. As much as possible to simplify the circuit and design on the basis of implementing core functions, the modules involved include: hardware mechanism design, physical memory allocation, code chunking principle, Linker script definition, package run file, operating system customization and so on. The architectural design that may be elaborated will include the above.

Please focus on the SOC Embedded software Architecture Design (Controller SOC firmware architecture) Series Blog:

One of SOC Embedded software Architecture design: system memory needs assessment

Soc Embedded Software Architecture design two: CPU without MMU design method of virtual memory management

Soc Embedded Software Architecture design Three: Code chunking (Bank) Design principles

Soc Embedded Software Architecture design four: Memory space planning allocation

The design of SOC Embedded software architecture: The reconfiguration of the operational program

Embedded: Memory-saving Software design tips

Copyright notice: This article Bo Master original articles, blogs, without consent may not be reproduced.

Soc Embedded Software Architecture Design II: No MMU design and implementation of CPU virtual memory management