STM32 Interrupt Control process

For STM32 Speaking (or the Timer2 case .), the external interrupt channel position 28 (number 35th priority) is TIME2 to the external device, but the TIME2 itself can cause an interruption of the interrupt source or event, such as Update event (overflow/underflow), input capture, output match, DMA request, etc.     All TIME2 interrupt events are the interrupt request to the STM32 kernel through a TIME2 interrupt channel, so how does STM32 handle and control TIME2 and its numerous, different, interrupted applications? 1. Because the CORTEX_M3 core has corresponding control words and control bits for each external interrupt channel, it is used for separate and total control of the interrupt channel. They include:

• Interrupt Priority Control Word: Pri_n (mentioned earlier)
• Interrupt allow setting bit: in Iser register
• Interrupt allow clear bit: in Icer register
• Interrupt suspension Pending (queued) position bit: In the ISPR register (similar to the interrupt channel flag bit)
• Interrupt suspension Pending (queued) bit clear: in the ICPR register (to clear the interrupt channel flag bit)
• Interruption (active) flag bit being serviced (active): In the IABR Register, (read-only, you can know which interrupt channel the current kernel is processing)

2. As peripheral devices, TIME2 itself also includes more specific interrupt controllers (BITS) that manage their own interrupts, which are primarily the allowable control bits for each of their different types of interrupts, and their respective interrupt flags (detailed in STM32 's manual). after understanding the above two points, we can fully, comprehensively and comprehensively understand the interruption process of TIME2 and how to control it. ① initialization Process

• The first step is to set the value of Prigroup in the Register AIRC, which specifies the number of preemptive priority and sub-priority in the system (the number of bits occupied in 4 bits);
• Set the register of the TIME2 itself, allowing the corresponding interrupt, as permitted by the UIE (time2_dier [0] bit)
• Set the preemptive priority and child priority (IP[28] for the TIME2 interrupt channel, in the NVIC Register group)
• Set allow TIME2 interrupt channel. One of the iser registers in the NVIC register group.

 

② Interrupt Response Process

• When the  UIE  condition of  TIME2  is established (update, overflow or underflow)   the hardware will  TIME2  itself in the register  uie   Interrupt flag and then request an interrupt service to the kernel via the  TIME2  interrupt channel.
• The kernel hardware now   the  Pending  flag of the  TIME2  interrupt channel (rather than the interrupt channel flag), which indicates that the  TIME2  has an interrupt request.
• If the current interrupt is not high enough to handle,time2 , then keep the  Pending  flag, of course the user can write  ICPR  in the software The corresponding bit in the register clears the interrupt.
• When the kernel is empty, start responding  TIME2  interrupts, enter  TIME2  interrupt service. At this point the hardware will  IABR  register the corresponding flag position bit,  indicates that the  TIME2  interrupt is being processed.   Simultaneous hardware removal  TIME2   Pending  flag bit.

③ Execution of TIME2 Interrupt service Program

• All TIME2 interrupt events are done in a TIME2 interrupt service program, so after entering the interrupt program, the interrupt program needs to first determine which TIME2 the specific event of the interrupt, and then transfer to the corresponding service code segment.
• Be careful not to forget to remove the interrupt flag bit for the specific interrupt event, and the hardware will not automatically clear the specific interrupt flag bit in the TIME2 register.
• If the TIME2 itself has more than 2 interrupt events, the order of their services is determined by the user-written interrupt service. In other words, the system cannot be set for the priority of multiple interrupts for the TIME2 itself. Therefore, when the user writes the service procedure, should according to the actual situation and the request, through the software way, the important interruption takes precedence to dispose.
• Of course you can also interrupt the service to handle only one of them, and then enter the interrupt again, processing the next.

④ interrupt return after the kernel executes the interrupt service, it enters the interrupt return process, which requires:

• The hardware will iabr the corresponding flag in the register to clear the other, indicating that the interrupt processing completed if the TIME2 itself also has an interrupt flag position, indicating that TIME2 there is an interruption in the application, the TIME2 Pending flag is reset to 1, waiting to enter the TIME2 interrupt service again.
• The above interrupt process is described in detail in the "ARM cortex-m3 authoritative guide", and it can be referenced with the timing diagram description.
• You can then set up and use the STM32 interrupt system correctly with the help of the Library of functions provided by ST.

 

STM32 Interrupt Control process