STM32 's Gpio

1. Gpio Introduction

• each universal IO Port has four 32-bit configuration registers, respectively :

-Gpiox_moder   : Mode Setting-Gpiox_otyper  : Type setting-GPIOX_OSPEEDR: Speed Selection-gpiox_pupdr   : Pull Down

• two 32-bit data storage, respectively :

-GPIOX_IDR  : Input data Register-GPIOX_ODR  : Output data register

• A 32-bit setting/reset Register :

-GPIOX_BSRR

• a 32-bit latch :

-Gpiox_lckr

• two additional function selection registers :

-GPIOX_AFRH: High 32-bit-GPIOX_AFRL: Low 32-bit

Each GPIO segment has 16 lead pins for use, and the pin designator is px0~px15, which differs from K60

2. Main electrical characteristics

• Output status: Pull-up drop, full push-pull output, open drain
• Output data from Data output register (GPIOX_ODR) or peripheral device (alternate function output) to IO pin
• Selectable clock speed per IO port
• Input status: Floating point, pull down, logic
• Input data from Data input register (GPIOX_IDR) or peripheral device (alternate function input) to IO pin
• Bit operation Register (GPIOX_BSRR) for bit operation on GPIOX_ODR

3. Input configuration

1. Output buffering disabled
2. Schmitt Trigger input activation
3. Pull-up drop-down resistor status depends on the value of the GPIOX_PUPDR register
4. IO port current status each AHB1 clock cycle is fed into the input data register
5. Read operation of the input data register obtains the status of the IO port

4. Output configuration

1. Output buffering enable:
   
   • Open-Drain mode: The output register is assigned a value of 0 active N-mos and 1 is in a high impedance state (P-mos will not be activated)
   • Push-Pull mode: The output register is assigned a value of 0 activates the N-mos output register is assigned a value of 1 P-mos
2. Schmitt Trigger input activation
3. The weak pull-up pull-down resistor is activated
4. IO port current status each AHB1 clock cycle is fed into the input data register
5. Read operation of the input data register obtains the status of the IO port
6. Read operation of the output data register obtains the state of the last write

5. Special function Configuration

1. Output configured for open-drain or push-pull
2. Output buffers are dominated by signals from peripherals
3. Schmitt Trigger input activation
4. The weak pull-up pull-down resistor is activated
5. IO port current status each AHB1 clock cycle is fed into the input data register
6. Read operation of the input data register obtains the status of the IO port

6. Operation of LED lamp with Gpio operation example (PF9 PF10)

//Base address for peripherals#define periph_base ((uint32_t) 0x40000000)/*!< Peripheral BASE address in the alias region< /c4>//base address for each bus#define apb1periph_base periph_base#define apb2periph_base (Periph_base + 0x00010000)#define ahb1periph_base (Periph_base + 0x00020000)#define ahb2periph_base (Periph_base + 0x10000000)//AHB1 Peripheral Extracts/*!< AHB1 Peripherals * *#define gpioa_base (Ahb1periph_base + 0x0000)#define gpiob_base (Ahb1periph_base + 0x0400)#define gpioc_base (Ahb1periph_base + 0x0800)#define gpiod_base (Ahb1periph_base + 0x0c00)#define gpioe_base (Ahb1periph_base + 0x1000)#define gpiof_base (Ahb1periph_base + 0x1400)#define gpiog_base (Ahb1periph_base + 0x1800)#define gpioh_base (Ahb1periph_base + 0x1c00)#define gpioi_base (Ahb1periph_base + 0x2000)#define gpioj_base (Ahb1periph_base + 0x2400)#define gpiok_base (Ahb1periph_base + 0x2800)

Example: a simple Gpio initialization

voidGpio_init (Gpiox_selectGpiox,Gpiox_pn_selectGPIOX_PN,Gpio_pull_typePullGpio_io_typeIoGpio_status_typeStatGpio_output_typeOtype) {Gpio_typedef*Gpiox; /*GetTheGpiox ' s Gpio_typedefstruct */Gpiox=bym_get_gpio_struct(Gpiox);RCC-Ahb1enr|= (1<< Gpiox); //EnableThe clock of Gpiox/*SetThe IO type of gpiox ' s pn * /    Gpiox-Moder&= ~ (3<< (GPIOX_PN *2)); //ClearThe Old registerData    Gpiox-Moder|= (IO << (GPIOX_PN *2)); //SetThe mode of Gpiox ' sPN/*SetThe IO ouput type of gpiox ' s pn * /    Gpiox-Otyper&= ~ (1<< GPIOX_PN); //ClearThe Old registerData    Gpiox-Otyper|= (Otype << GPIOX_PN); //SetThe output type of gpiox ' s PN/* PullDown or pulling up or nothing forGpiox ' sPN */Gpiox-pupdr&= ~ (3<< (GPIOX_PN *2)); //ClearThe Old registerData    Gpiox-pupdr|= (Pull << (GPIOX_PN *2)); /* onlySet the PIN status when the ' IO ' value is 'Bym_gpo '*/if(IO = =Bym_gpo)    {Gpiox-ODR&= ~ (1<< GPIOX_PN);Gpiox-ODR|= (stat << GPIOX_PN); }   }

Example: Get IO Port status

/*  * Get GPIO pin status */uint32_t gpio_get(GPIOx_SELECT gpiox, GPIOx_pn_SELECT gpiox_pn){    *GPIOx;    /* Get the GPIOx‘s GPIO_TypeDef struct */    = BYM_GET_GPIO_struct(gpiox);    return ((GPIOx->& (1<< gpiox_pn));}

definition of the//enumeration variable/ * Select enumeration of GPIO segments * /typedef enum{Bym_gpioa, Bym_gpiob, BYM_GPIOC, Bym_gpiod, Bym_gpioe, Bym_gpiof, Bym_gpiog, Bym_gpioh, Bym_gpioi, BYM_GPIOJ, B Ym_gpiok,}gpiox_select;/ * GPIO PIN Number Selection enumeration * /typedef enum{bym_px0, bym_px1, bym_px2, Bym_px3, Bym_px4, bym_px5, bym_px6, bym_px7, bym_px8, bym_px9, bym_px10, bym_px11, bym_px12, bym_px13, bym_px14, Bym_px15,}gpiox_pn_select;/ * Enumeration of Pull-up dropdown * /typedef enum{bym_no_pull, bym_pull_up, Bym_pull_down,} Gpio_pull_type;/ * Output Mode enumeration * /typedef enum{bym_push_pull, Bym_open_drain,} Gpio_output_type;/ * IO PIN Multiplexing Mode enumeration * /typedef enum{BYM_GPI, Bym_gpo, Bym_gpalt, Bym_gpana,} Gpio_io_type;/ * PIN Status enumeration When PIN is set to output * /typedef enum{bym_low_level, Bym_high_level,} Gpio_status_type;/ * Get the GPIO ' s gpio_typedef struct * /#define BYM_GET_GPIO_STRUCT (gpiox) \((Gpio_typedef *) (Ahb1periph_base + (Gpiox *0x400)))

7, different additional peripheral functions of the GPIO port

AF0     systemAF1     tim1/tim2af2     tim3~tim5af3     tim8~tim11af4     i2c1~i2c3af5     spi1~spi2af6     Spi3af7     usart1~usart3af8     usart4~usart6af9     can1/can2,tim12~tim14af10    otg_fs,otg_hsaf11    ETHAF12    fsmc,sdio,otg_hs (1) AF13    DCMIAF14    AF15    eventout

8. Pin Latches

• Pin latches to the GPIO pin status lock After a series of operations on the register until the next CPU reset or the GPIO PIN module is reset to allow the state to change

• The procedure is done by writing to the Gpiox_lckr register.

WR LCKR[16] = ‘1’ + LCKR[15:0]WR LCKR[16] = ‘0’ + LCKR[15:0]WR LCKR[16] = ‘1’ + LCKR[15:0]/* 上面三步是要求的操作步骤 */RD LCKRRD LCKR[16] = ‘1/* 上面两步是为了保证gpio管脚状态被成功的设置了 */

9, a GPIO port initialization process

• Set the GPIO segment clock on (all chips on-chip peripherals need to turn on the clock first), Ahb1enr (Gpio belongs to the AHB1 bus)
• Select the Gpio pin number to be set for this segment
• Mode settings for its registers, including input/output mode, speed, pin multiplexing, pull-down, etc.

10, and 51 series 8-bit MCU IO port of the main difference

• Different points:

  • Optional pull-up drop-down resistor
  • Programmable IO Frequency
  • Can be latched
  • Explicit input and output status

• Same point:

  • can set peripheral functions
  • All have push-pull, open-drain, normal IO port three modes

STM32 's Gpio