STM32 System and Timer Clock configurations
I ' ve started writing some software to drive a series of TLC5940 Channel LEDs Driver chips on an ST stm32f407 Microcontro Ller.
I previously had code working on a Atmel microcontroller, but obviously and the change of hardware comes
The need for re-writing some of the lower peripheral configuration and application code.
The both main requirements for driving the TLC5940 chip from a microcontroller is:
- The grayscale clock
- A Serial Data bus
The microcontroller ' s SPI Port is a well suited to delivering data to the TLC5940 even though it's not officially an ' SPI ' Device. For the grayscale clock I has decided to use the STM32 's timer modules to automatically provide the BLANK and GSCLK Signa ls. basically, the blank signal is used to reset the grayscale counter inside the TLC5940, and depending on the Desir Ed LED brightness resolution, we wait a certain number of GSCLK cycles before generating a BLANK pulse to reset the TLC594 0 ' s internal counter. both These signals has timing requirements placed on them, so we need to understand exactly ho W The STM32 ' s timer modules function. And before we can do this, we also need to understand the clock source that drives the timers (in my case, the internal SY Stem clock). my board uses an external 8MHz crystal oscillator as its clock source, and although I believed I had it Configured correctly, bit without measuring it, I couldn ' t be sure. Well ... I could has flashed an LED at a human-measurable speed, like 1Hz, but that's not as fun as delving right into the core and working out to T He timer modules. :P the Maximum frequency specified by ST for this device are 168MHz, so the frequency I'll configure the Dev Ice for. To begin with, the 8MHz clock was the ' High speed External ' clock signal, or HSE as it was known, enters the microcontroller Through its osc_in/osc_out pins, before being sent to the ' Phase Lock Loop ' (PLL) module to is divided and multiplied by Several pre-scalers to provide the ' System clock ' (SYSCLK), the ' Advanced High-performance Bus ' (AHB) clock, and the " Advanced Peripheral Bus ' clocks (APB1 and APB2). There is several other clocks configured by the ' Reset and Clock Control ' (RCC) peripheral, but these aren ' t directly rel Ated to the Timer modules I am using. the C source files in The stm32f4xxstdperiph Library where the system Clock is configured include:
- system_stm32f4xx.c -the PLL register value #DEFINEs and initialisation code is found here
- stm32f4xx.h -The HSE frequency is defined at the start
The Systemcoreclock variable in the first of the "the" and "above is calculated using the" following "equations found in The RM0090 Reference Manual:
- F (VCO clock) = f (PLL clock input) x (PLLN/PLLM)
- F (PLL general clock output) = f (VCO clock)/PLLP
These equations describe what's happening in the hardware. First, the HSE clock signal is divided by the Pllm division factor. The result from this
must be between 1-2mhz, but a value of2MHz is recommended to limit PLL jitter. This pre-scaled signal then enters the Main PLL module where it's multiplied by Plln, the VCO multiplication factor, to P Rovide a signal between 432MHz, and then divided-down by the PLLP factor-produce the systemcoreclock with a Frequency no greater than 168MHz.
My initial setup used the following configuration:
stm32f4xx.h:
- #define Hse_value ((uint32_t) 8000000)
system_stm32f4xx.c
- #define PLL_M 8
- #define PLL_N 336
- #define PLL_P 2
However after noticing the mention of increased clock jitter, I decided to change Pll_m to ' 4 ', pll_n to ' 168 '. All the PLL parameters above is placed into the ' RCC PLL Configuration Register ', rcc_pllcfgr.
Now, with the settings-the core clock determined and initialised into code, I needed A-to view these signals, and Luckily for me the nice people at ST has provided hardware that can select from various internal clock signals, Pre-scale them, and present them for viewing on the external pins, MCO1 and MCO2 which is the ' microcontroller Clock Output ' pins. These is configured in the ' RCC Clock Configuration Register ' rcc_cfgr using the Mcox bits for selecting the desired sig NAL, and the mcoxpre bits to scale the signal by a factor of between 1 and 5.
Using the Peripheral library commands below, I ' ve selected the HSE for MCO1, and Sysclk divided by 5 for MCO2. This should provide signals of 8MHz and 33.6MHz if my configuration is correct.
- Rcc_mco1config (Rcc_mco1source_hse, rcc_mco1div_1);
- Rcc_mco2config (RCC_MCO2SOURCE_SYSCLK, rcc_mco2div_5);
And viewing these signals in the images below we can see that it's roughly the case. The 0.8% error in the SYSCLK (blue Ch2) signal are either due to the actual signal being slightly out due to the PLL Scalin G system, or possibly the limitations of my cheap 100MHz ' scope (I'll test this tomorrow on some old (but high-end) Le C Roy and Tektronix 500MHz ' scopes at work tomorrow. Next I ' m moving on to confirming my gsclk and BLANK timer configuration was as I need it to be.
UPDATE:
I ' ve taken some measurements with the scopes @ work and they appear to agree with the 8MHz result, but definitely show th E 33.6MHz sysclk (within the margin of error):
Now that I ' ve verified my system's core clock is functioning as expected,
I can move onto configuring the clock modules to produce the desired BLANK and GSCLK signals to control the TLC5940 chips.
Using the SYSCLK signal, the ' Advanced High-performance Bus ' (AHB) clock frequency is set via a prescaler.
In this case I am using the maximum frequency of the AHB by setting the Prescaler to divide by 1.
The ' Advanced Peripheral Bus ' clocks (APB1 and APB2) is generated from the AHB via their associated prescalers.
They has maximum frequencies of 84MHz respectively,
So my APB1 prescaler are set to ' 4 ' and APB2 Prescaler are set to ' 2 '.
The internal signal that can being selected as the Timer peripherals ' clock is the APB1 clock.
however ...
And this is a important part-to-take note of:
While the APB1 signal provides the clock for numerous peripherals including the timer modules,
The timers can receive a faster clock if the APB1 prescaler is set to anything and other than ' 1 '. The manual states:
- If the APB Prescaler is 1, the timer clock frequencies be set to the same frequency as, the APB domain to which th E timers is connected.
- Otherwise, they is set to twice (x2) The frequency of the APB domain to which the timers is connected.
Since the APB1 prescaler I am using is ' 4 ' and the AHB clock are 168MHz, the internal clock presented to the timer modules is actually (168/4) * 2 = 84MHz.
Inside the TIMX modules there is three main clock signals:
- ck_int-the internal clock before prescaling
- Ck_psc-the clock signal after being divided by the Prescaler
- Ck_cnt-the counter clock, which generates pulses every time the prescaler counter overflows
Note that while there is different clock signals (internal clock, external clock, internal triggers, etc)
That can is used as the main input to each of the timer module, since I don ' t need to synchronise to external signals,
I'll use the default internal clock, APB1.
The internal clock signal APB1 is fed into my main timer module TIM3.
This module is used to provide both the GSCLK signal a external GPIO pin,
and also to trigger/clock the slave TIM4 module which would provide the BLANK pulses.
Initially I intend to has the TIM3 setup for it fastest possible rate,
And then configure the output for the desired GSCLK frequency once both signals is synchronised correctly.
I am using a prescaler divide factor of 1 (TIM3_PSC = 0), so CK_PSC = Ck_int = APB1 * 2 = 84MHz.
each TIM module from TIM2 to TIM5 (and some others) can is used as a ' master ' or a ' slave ' to generate signals or re Act to them in various ways. For instance, I can use TIM3 as a master that generates a trigger pulse every time the counter reaches a specific value. I could then use this trigger pulse as the main clock signal in another timer module. the the "I intend to use TIM3" is To use it ' Update Event ' as its external trigger signal (TRGO) which generates a "pulse every time its counter ' ov Erflows ', or reaches the upper limit which is set in the ' Auto Reload Register ' (ARR). the TIM3 Counter is conf Igured in ' upcounter Mode ' which means, every rising edge of the counter clock causes the counter to increment until I T reaches the ARR value. when it reaches this upper limit, it generates a ' Update Event ', Uev, which causes the counter to reset to ' 0 '. Each Uev pulses the trigger signal, so if ARR was set to ' 1 ', the counter moves from 0 to 1, geneRates a trigger pulse, resets the counter to 0, and the process repeats forever. this two-count overflow acts as a di Vide-by-two on the ck_cnt signal. Therefore, our TIM3 Master trigger signal is 84MHZ/2 = 42MHz.
This trigger is passed to TIM4 on the Internal trigger network, which, when these II specific timers is used, is the I Nternal Trigger 2 Signal (ITR2).
Returning to the original task of providing grayscale clock and blanking pulse signals for the TLC5940, the both timer Modu Les now need to being configured to generate these signals on their Output Compare pins.
For the GSCLK signal, the TIM3 output Compare Channel 1 (OC1) signal are configured to toggle its output every time the Cou Nter matches the desired value;In the case ' 1 '.This essentially means, it is synchronised with the TRG0 signal at half the frequency.
For the BLANK signal, we need to is able to synchronise the signals with a phase shift so that the desired number of GSCLK Pulses is generated before a blanking pulse is generated.
To does this , the TIM4 counter are configured in ' Centre Aligned ' mode,
So, it counts up to the ARR, value and then counts down to zero and repeats. The TIM4 OC1 signal is configured as a PWM signal this is set when the counter are less than OC1 ' s capture/compare registe R (CCR1) value, where:
Due to internal timing, the TIM3 OC1 signal are given a slight phase shift relative to the TIM4 OC1,And the result is, the number of rising edges between consecutive blanking pulses is the desired number (Gsclk_count). I ' m still not exactly sure what, so I'll need to investigate the origin of this phase shift, but is now I'm happy that It ' s there.
The timing for each timer module, and the resulting signals seen by the TLC5940 chip is shown below in Fig.1.
Here Gsclk_count are set to ' 2 '.Note that for TIM4, the Ck_int is TIM3 ' s TRG0.
Figure 1:tim3, TIM4, and the TLC5940 Signal ConfigurationI ' ve experimented with changing the TIM3 prescaler to adjust the GSCLK frequency, different numbers of gsclk_pulses. Below Fig. 2 and fig. 3 show scope captures of different configurations:
Figure 2:GSCLK = 21MHz, Gsclk_count = 2
Figure 3:GSCLK = 82kHz, Gsclk_count = 4Now the timing of the TLC5940 GSCLK and BLANK signals has been configured and is easily adjustable for the desired Frequency and intensity resolution, it ' s time to move onto the TLC5940 ' s serial data interface.
STM32 System and Timer Clock configurations
