The difference between wire and Reg in Verilog HDL

Url:http://www.cnblogs.com/tureno/articles/2218669.html

Wire represents a pass-through, where the input is changed, and the output is immediately and unconditionally reflected (e.g., simple connections to and from doors).

Reg indicates that a trigger must be in order for the output to reflect the state of the input.

Reg corresponds to a storage unit, which is equivalent to a physical connection. Reg indicates that there must be a trigger, no input can keep the original value, but not directly the actual hardware circuit corresponding.

The difference between the two is that the register type data is retained for the last assignment, and the Linetype data needs to be continuously driven. Wire is used in continuous assignment statements, while Reg is used in procedure assignment statements (initial, always). Wire without a drive connection with a value of Z,reg the default initial value is an indeterminate value of X.

In a continuous assignment statement, the evaluation to the right of the expression can immediately update the left side of the expression. In understanding, the equivalent of a logic followed by a straight line, the logic corresponds to the right side of the expression, and this line corresponds to the wire. In a procedure assignment statement, the calculation of the right side of the expression is lowered to a variable in a certain condition, and the variable can be declared as a reg type. Depending on the trigger condition , the procedure assignment statement can model different hardware structures: If this condition is the rising or falling edge of the clock, then the hardware model is a trigger; if the condition is a high or low level of a signal, then the hardware model is a latch If this condition is the change of any operand to the right of the assignment statement, then the hardware model is a combinatorial logic.

For combinational logic output variables, you can use assign directly. That is, if you do not specify a reg type, then the default is 1-bit wire type, so you do not need to specify a 1-bit wire type variable. Of course the wire type is specifically specified, which may be multi-bit or for making the program easy to read. a wire can only be assigned by assign, and Reg can only be assigned in initial and always.

The input port can be driven by the Wire/reg, but the input port can only be wire, the output port may be the Wire/reg type, the output port can only drive wire,if the output port is assigned a value in the process block is a reg type, if the outside of the procedure block assignment is net type (Wire/tri). using the keyword inout to declare a bidirectional port, the InOut port cannot be declared as a reg type, only a wire type.

The default signal is wire type, and the Reg type must be declared. By default, this means that the output signal is a wire when it is declared as outputs. If the module internal signal, must be declared as wire or Reg.

For the always statement, the assignment should be declared as Reg, the continuous assignment of assign with wire.

The signal type determination method for module invocation is summarized as follows:

• Signals can be divided into port signals and internal signals. The signal in the port list is the port signal, and the other signal is the internal signal.

• For port signals, the input port can only be net type. The output port can be either a net type or a register type. If the output port is assigned a value in the process block, it is the register type, or the net type if the value is assigned outside the procedure block, including the instantiation statement.

• The internal signal type is the same as the output port and can be a net or register type. The method of judging is also the same as the output port. The register type if the value is assigned in the procedure block, or the net type if the value is assigned outside the procedure block.

• If the signal needs to be assigned in a process block, it needs to be assigned outside the procedure block. This situation is likely to occur, such as a decision signal. An intermediate signal conversion is required.

The following is a list of common errors and corresponding error messages (Err message)

• Use a procedure statement to assign a signal to a net type or to a forgotten claim type.

Info: illegal. Assignment.

• Connect the output of the instance to a signal declared as the register type.

Information:<name> has illegal output port specification.

• Declare the input signal of the module as the register type.

Info: Incompatible declaration, <signal name> ...

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The difference between wire and Reg type:

Wire type data is commonly used to represent the combined logic signals specified with the Assign keyword. The input and output port type of the module is the wire type by default. The default initial value is Z.

The register type represented by the Reg type. The assigned signal within the Always module must be defined as a Reg type, which represents the trigger.

The default initial value is X.

reg corresponds to a storage unit, which is equivalent to a physical connection.

The physical data of variables in Verilog is divided into linear and register types. These two types of variables are defined with a bit width set, and the default is 1 bits. Each bit of a variable can be a 0,1,x,z. where x represents a variable that is not pre-initialized or is a conflicting linetype variable caused by two or more drives attempting to set it to a different value. Z represents a high-impedance state or a floating volume.

The Linetype data includes several types such as Wire,wand,wor, when driven by more than one excitation source, different linetype data have their own resolution to determine their final value.

The difference between the two is that the register type data is retained for the last assignment, and the Linetype data requires a continuous drive

The input port can be driven by net/reg, but the input port is only net, such as a = B & C, the input port A can only be net type, but its driver b,c can be net/reg type, the output port can make the Net/reg type, the output port only drives net, such as a = B & Amp C, the output port of the module b,c can be net/reg type, but they drive a must be net type, if the output port in the process block (always/initial) is assigned to a reg type, if the outside of the procedure block assignment is net type. Using the keyword InOut to declare a bidirectional port, the InOut port cannot be declared as a register type, only a net type.

Wire Express, that is, as long as the input changes, the output is immediately and unconditionally reflected; Reg indicates that there must be a trigger and the output will reflect the input.

The default is 1-bit wire type without specifying it. specifically specifies the wire type, which may be multi-bit or for making the program easy to read. A wire can only be assigned by assign, and Reg can only be assigned in initial and always. Wire is used in continuous assignment statements, while Reg is used in procedure assignment statements.

In a continuous assignment statement, the evaluation to the right of the expression can immediately update the left side of the expression. In understanding , the equivalent of a logic followed by a straight line, the logic corresponds to the right side of the expression, and this line corresponds to the wire. In a procedure assignment statement, the calculation of the right side of the expression is lowered to a variable in a certain condition, and the variable can be declared as a reg type. depending on the trigger condition, the procedure assignment statement can model different hardware structures: If this condition is the rising or falling edge of the clock, then the hardware model is a trigger; if the condition is a high or low level of a signal, then the hardware model is a latch If this condition is the change of any operand to the right of the assignment statement, then the hardware model is a combinatorial logic.

the variable of wire type is generally a conductor;

The REG variable has two cases in the Always block:
Always after the sensitive table is (a or B or C) Form, that is, without the clock edge, integrated or combinatorial logic
Always after the sensitive table is (Posedge clk) Form, that is, with the edge, the general is the timing logic, will contain triggers (flip-flop)

in the design, the input signal in general you do not know whether the upper level is the register output or the combination of logic output, then for this level is a wire, that is, cable type. And the output signal is your own decision is the register output or combination logic output, wire type, Reg type can be. But in general, the entire design of the external output (that is, the output of the top-level module), the requirements are register output, more stable, fan-out ability is also good.