The flow of power analysis in IC design

First of all, the scope of this article, in this article, is the use of Synopsys design process, the digital circuit power analysis, the generation of power analysis report process. The analyzed object is the power analysis that precedes the layout after the logical synthesis, and the power analysis after the layout is routed.

   synopsys the tools used to do power analysis are: Primetime PX, Prime Rail. PTPX can be used to estimate power consumption after a logical synthesis. PrimeTime px is a tool integrated in the PrimeTime, although he can do power analysis, but not sign-off tools. True to the end of the Sign-off, if the demand for power is very high, still need to use prime rail analysis, so we just use the primetime px to do power analysis is enough.      is the process of power analysis after layout and routing and logic synthesis. I. Power analysis after logic synthesis   The files used are: 1. Verilog files after logic synthesis                   2. Constraint files used in static time series analysis                   3. RTL simulation files, I use a VCD, after all, the standard of each emulator support ~                  4. Library file with power consumption information. db, this library file can report a cell in a library to see if there are any.     With these files, you can do power analysis. Let's talk about the flow of power analysis: 1. Allows the power analysis function set POWER_ENABLE_ANALYSIS2. Set Analysis mode     set Power_analysis_mode. There are two types of his pattern, one is average mode, no simulation file, and the other is time-based mode, which determines activity factor according to the timing simulation file. 3. Read in the design and library file  4. Specifies operating condition5. Timing Analysis  update_timing6. To get activity data if it is an RTL-level Web table file, use-rtl to tell PT that the previously specified VCD file was before the layout was routed. If the VCD is Zero_delay simulation, that is pure functional simulation words, should be home-zero_delay option. If all refer toBy default, PT is Gate-level. 7. Set Power analysis Options set_power_analysis_options:-static_leakage_only option of the Set_power_analysis_options command is Supported @          the averaged power analysis mode.       -waveform _interval,-cycle_accurate_cycle_count,-cycle_accurate_clock,-waveform_format,-          Waveform_output,-include, and-include_groups options are supported only in the time-        &N Bsp  based Power Analysis mode.8. Power Analysis  update_power9. Generate power Analysis report Report_power to illustrate, PTPX is an enhancement to primetime, with just one PT script, and I'll share my pt script:  file:pt.tcl ######### ###################################   Set The Power analysis mode########################################## #set Power_enable_analysis True;set Power_analysis_mode averaged;############################################    read and link the gate level netlist########################################## #set Search_path ".. /source db././result "Set Link_library" typical.db "set Target_library" Typical.db "Read_verilog jnd_90s.vset top_name Jndcurrent_design jndlink############################################   Read SDC and set transition time or Annotate parasitics########################################## #read_sdc pt_con.tcl ######################### ###################   Check, update, or report timing########################################## #check_ timingupdate_timingreport_timing  ############################################  read Switching Activity file########################################## #read_vcd-rtl Jnd_all.vcd-strip_path Testbenchreport_ switching_activity-list_not_annotated ############################################   Check or update or Report power########################################## #check_powerupdate_powerreport_power-hierarchy  two. Power analysis after layout and cabling now PTPX also supports multi-voltage domain power analysis and provides a sample script that describes the multi-clock domain using UPF, called Unified Power format. Not introduced here. # Read Libraries, DEsign, enable power analysis# and link designset power_enable_analysis trueset link_library slow_pgpin.dbread_verilog POW er_pins.vlink # Create back-up Power netscreate_power_net_info vdd_backup-powercreate_power_net_info vss_backup -gnd# Create Domain power netscreate_power_net_info t_vdd-power-switchable \-nominal_voltages{1.2}-voltage_ranges{ 1.1 1.3}create_power_net_info a_vdd-powercreate_power_net_info b_vdd-power# Create domain ground netscreate_power_net _info t_vss-gndcreate_power_net_info a_vss-gndcreate_power_net_info b_vss-gnd# Create Internal Power netscreate_power _net_info int_vdd_1-power \-nominal_voltages{1.2}-voltage_ranges[1.1 1.3} \-switchablecreate_power_net_info INT_VDD _2-power \-nominal_voltages{1.25}-voltage_ranges{1.1 1.3}create_power_net_info int_vdd_3-power \-nominal_voltages{ 1.2}-voltage_ranges{1.1 1.3}create_power_net_info int_vdd_4-power# create power Domainscreate_power_domain Tcreate_ Power_domain A-object_list[get_cells Pd0_inst]\-power_down-power_down_ctrl[get_nets A] \-power_down_ctrl_sense 0create_power_domain b-object_list [Get_cells PD1_inst]\- power_down# Connect Rails to power domainsconnect_power_domain t-primary_power_net T_VDD \-primary_ground_net t_ Vssconnect_power_domain a-primary_power_net a_vdd \-primary_ground_net a_vss \-backup_power_net vdd_backup \-backup_ Ground_net vss_backupconnect_power_domain b-primary_power_net b_vdd \-primary_ground_net b_vss # Set voltages of Power netsset_voltage 1.15-object_list{t_vdd a_vdd b_vdd}# Read SDC and other timing or power assertionsset_input_transit Ion 0.0395 [All_inputs]set_load 1.0 [All outputs]# Perform timing analysisupdate_timing# Read switching ACTIVITYSET_SWITC hing_activity...set_switching_activity......report_power   three. Reports   a standard report: Power Group Power Power Power Power (%) Attrs---------------------------------------------------------------io_pad 0.0000 0.0000 0.0000 0.0000 (0%) Memory 0.0000 0.0000 0.0000 0.0000 (0.00%) Black_bOx 0.0000 0.0000 0.0000 0.0000 (0.00%) clock_network 0.0000 0.0000 0.0000 0.0000 (0.00%) Register 8.442e-05 1.114e-05 9.20 8e-09 9.557e-05 (29.97%) icombinational 0.0000 0.0000 0.0000 0.0000 (0.00%) sequential 0.0000 0.0000 0.0000 0.0000 (0% ) Attributes----------i-including driven Register powerinternal switching leakage total clockpower power power (%) Attrs---------------------------------------------------------------CLK 1.813e-04 4.199e-05 4.129e-10 2.233e-04---------------------------------------------------------------Estimated clock1.813e-04 4.199e-054.129e-102.233e-04 (70.03%) Net Switching power = 5.313e-05 (16.66%) cell Internal power = 2.657e-04 (83.33%) cell L Eakage power = 9.627e-09 (0.00%)---------Total Power = 3.188e-04 (100.00%)   Report on gated clocks: report_clock_gate_savings*** Report:clock Gate Savingspower_mode:AveragedDesign:mydesignVersion: D-2009.12date:thu Oct 12:08:20 2009****************************************------------------------------------------------------------------clock:clk+ Clock Toggle rate:0.392157+ number of registers:19262+ number of clock gates:12+ Average clock Toggle rate @ registers:0.305872+ Average Toggle Savings at R egisters:22.0%------------------------------------------------------------------Toggle Savings number of% Ofdistribution Registers registers------------------------------------------------------------------100% 0 0.0%80% -100% 0.4%60%-80% 5660 29.4%40%-60% 0 0.0%20%-40% 8 0.0%0%-20% 0 0.0%0% 13518 70.2%--------------------------- ---------------------------------------

Flow of power analysis in IC design