The sixth week Experiment Report of information security system design

The sixth chapter, the storage level structure

Memory system: A hierarchical structure of memory devices with different capacity, cost, and access times. Basic properties of computer programs: locality. Programs with good locality tend to access the same or neighboring collections of data items again and again, preferring to access data items at higher levels in the memory hierarchy, and therefore run faster.

First, storage technology

(1) Random access memory (RAM)

Static RAM: Used as cache memory, each bit stored in a bistable memory unit.

Dynamic RAM: A frame buffer used as the primary storage and graphics system.

The traditional DRAM:

1. The information flows into/out of the chip through a foreign connector called a PIN, each pin carries a 1-bit signal.

2. Each DRAM signal is connected to a circuit called a storage controller, and the circuit transmits 8 bits at a time. CAS requests to share the same DRAM address pins.

Accessing main memory

Bus: The data stream is transmitted between the processor and the DRAM via a shared electronic circuit called a bus.

Bus transaction: The process of data transfer between CPU and main memory.

I/O Bridge: translates the electronic signal of the system bus into the electronic signal of the memory bus

(2) Non-volatile memory (ROM)

Power loss, DRAM and SRAM will lose information: ROM.

Programmable ROM (PROM): can only be programmed once. Prom Each storage unit has a fuse that can only be fused once with a high current.

Erasable programmable Rom: ultraviolet light shines through the window, the EPROM is cleared to 0, the number of erased and reprogrammed is 1000 times.

Electronic erasable Rom: does not require a physically separate programming device, so it can be programmed directly on the printed circuit card and can be programmed in the number of 10^5.

Flash Memory: Provides fast and durable non-volatile storage for a large number of electronic devices.

(3) disk storage

Disk Construction: The disk is composed of platters, the surface is covered with magnetic recording material, the center has a rotatable spindle, the rotation rate of about 5400-15000 per minute.

Disk Capacity determinants:

Recording density: The number of bits that can be placed in an inch of a track.

Track density: The number of tracks that can be in the one-inch radius from the center of the disc

Surface density: The product of recording density and track density.

Logical Disk BLOCK: A modern disk treats the construction of the disk face as a logical block sequence of a B sector size, and the disk controller maintains a mapping between the logical block number and the actual disk sector.

Connect to I/O devices: All I/O devices are connected to the CPU and main memory via the I/O bus.

There are three different types of:

Universal Serial Bus: A wide range of usage standards for connecting various peripheral I/O devices.

Graphics card (or adapter): Contains hardware and software logic, representing the CPU on the display of the image.

Host Bus adapter: Connect one or more disks to the I/O bus, using a communication protocol defined by a special host bus interface.

(4) Storage technology trends

Different storage technologies have different price and performance tradeoffs. The price and performance attributes of different storage technologies vary at a very different rate. DRAM and disk performance lag behind the performance of the CPU.

Second, the local nature

Locality of the reference to the program data:

Time locality: The memory location that has been referenced once will be referenced more than once in the future.

Spatial locality: If the location of a memory is referenced, then the location near him will also be referenced in the future.

Three, memory hierarchy structure

(1) Caching in the memory hierarchy

A cache is a small, fast storage device that acts as a buffer zone for data objects stored in larger, slower devices. Each layer of memory is divided into contiguous pieces of data, called blocks, with unique objects and names for each block. Data is always copied back and forth between the K-level and the k+1 layer with the block size as the transmission unit.

Types of Cache Misses

1. Mandatory Miss/Cold miss: The K-tier cache is empty (cold cache), only a transient state, does not occur after repeated access to the memory to make the cache warm after the stable state.

2. Conflict misses: Block I of section k+1, must be placed in block K (i mod 4), this restrictive placement policy causes conflict misses.

Four, cache memory

Each storage address of a computer system has m-bits, which form m=2^m different addresses. The cache is organized into an array of s=2^s cache groups, each containing an e cache line, each consisting of a b=2^b byte block, a valid bit, and a t=m-(b+s) tag bit that uniquely identifies the block stored in the cache row.

(1) Direct-mapped cache

Only one row per group (e=1) of cache is called direct mapping cache. The cache determines whether a request is hit, and then extracts the requested word into three steps: Group selection, row matching, and word extraction.

(2) Full-attached cache

Group selection in a fully connected cache: There is only one group and no group index bits.

Row matching and word selection in a fully connected cache: the same as the group-attached cache, but much larger, so it is only suitable for small caches, such as the translation backup buffers in virtual storage systems.

(3) Performance impact of cache parameters

No hit: Number of misses/number of references
Hit ratio: 1-no hit

Factors that affect performance

Impact of cache Size: Larger caches may improve hit ratios, but making large memory runs faster is harder.

Block size impact: Larger blocks can take advantage of possible spatial locality in the program to help improve the hit ratio, but larger chunks mean less cache lines and damage time locality.

The effect of the degree of coupling: a greater degree of coupling (greater E value) has the advantage of reducing the likelihood that the cache is jitter due to conflict misses, but at a higher cost.

Impact of Write policies: write-through caches are easy to implement, and can be used in cache-independent write buffers to update memory with little overhead. The write-back cache causes fewer transfers, allowing more bandwidth to the memory to be used to perform DMA I/O devices. A lower layer is more likely to use write-back.

Five, learning feelings

This course emphasis on more words, patience to learn.

Resources

In-depth understanding of computer systems

The sixth week Experiment Report of information security system design