Tiny6410 NAND flash Drive

First, the characteristics of NAND flash

The s3c6410 NAND Flash controller has the following features

1, since the import mode: After the reset, the boot code is fed into the 8KB steppingstone, the boot code is moved, the boot code will be executed in Steppingstone. During import, the NAND Flash Controller does not support ECC correction.

2. NAND FLSH controller i/f: Supports 512-byte and 2KB pages

3, Software mode: The user can directly access the NAND Flash controller, this feature can be used for reading/sassafras/programming NAND flash memory.

1) Write command register =nand flash memory command cycle

2) write address register =nand flash memory address period

3) Write Data Register = Write data to NAND flash memory (write cycle)

4) Read Data Register = data from NAND FLASH memory (read cycle)

5) Read primary ECC register and standby ECC Register = Read data from NAND flash memory

4. Interface: 8-bit NAND flash memory Interface Bus

5, Hardware: ECC generation, detection and marking (software correction)

6, support SLC and MLC NAND Flash Controller: 1-bit ECC for slc,4 bit ECC for MLC NAND Flash

7, Special function register I/F: Support byte/half word/Word data access ECC data register, use Word to access other registers

8, Steppingstone i/f: Support byte/half word/Word data access

9, 8KB internal SRAM buffer steppingstone, after the NAND flash boot can be used for other purposes

The Tiny6410 Development Board uses the type of NAND flash for the MLC size 2G, model k9ga08u0e-s

Second, drive design

Step one: Set the control register for NAND Flash

The s3c6410 data sheet shows that the control register for Nnad Flash is nfconf

Register Address

Nfconf 0x70200000

In the NFCONF register, the main use of the Tacls, TWRPH0, TWRPH1, these three variables. These three variables are used to configure the timing of the NAND flash. Through the timing diagram

By Tacls, the duration of Cle/ale effective to nwe is valid. The effective duration of the TWRPH0 bit nwe. TWRPH1 the duration between nwe invalid to Cle/ale invalid. These times are in HCLK units.

The K9F2G08U0E data sheet (e.g.) indicates that Twp and TWRPH0 correspond, (TCLS-TWP) corresponds to Tals, TCLH corresponds to TWRPH1.

The value given by k9f2g08u0 is the minimum value. Therefore, the value is as long as the minimum value can be satisfied. So here I will tacls, TWRPH0, TWRPH1 values for 0x2, 0xF and 0x7 respectively.

Therefore set the value of the nfconf Register to ((0X2<<12) | (0xf<<8) | (0x7<<4))

Step two: Enable NAND FLASH

Through the s3c6410 verse manual you can know that the register for NAND Flash is Nfcont

Register Address

Nfcont 0x7020004

The description of the register indicates that the BIT0 bit of the Nfcont is controlled by NAND flash. Therefore, the value of the 0th bit of Nfcont is set to 1 even if NAND FLASH is available.

Step three: Read operation (page read)

If the reading operation is mainly divided into five steps.

1, Hair piece selection: That is, set Nfcont bit1 0

2, issued the command: 0x00, that is, to write 0x00 Nfcmd

3, send address: By the known address needs to be divided into 5 clock cycles to send, that is, to nfaddr write address, because NFADDR can only accept 8bit of data at a time

4, read the command: 0x30, that is, to Nfcmd write 0x30

5, read continuously 2048 bytes, that is, read Nfdata register 2048 times.

Fourth Step: Copy

Call the NAND Flash read operation until the. bin file is completely copied from NAND flash into DRAM.

Fifth Step: Coding Run

The main code is implemented as follows

Start. S.global _start_start//The peripherals told Cpuldr R0, =0x70000000orr r0,r0, #0x13mcr p15,0,r0,c15,c2,4//official watchdog LDR R0,=0x7e004000mov R1, #0str r1,[r0]//Settings Stack ldr sp,=0x0c002000//open icaches#ifdef config_sys_icache_offbic r0,r0, #0x00001000 #elseorr r0,r0,# 0X00001000MCR p15,0,r0,c1,c0,0x00001000#endif//Set clock bl clock_init//initial swap SDRAMBL sdram_init//initialize NAND FLASHBL nand_init/ /relocation, copy the code, data to his link. ADR R0,_start    @_start's current address Ldr R1,=_star    @_start's link address Ldr r2,=bss_startsub r2,r2,r1cmp r0 , R1beq CLEAN_BSSBL copy2ddrcmp r0, #0bne halt//clear BSS, clear BSS corresponding memory 0 clean_bss:ldr r0,=bss_startldr R1,=bss_endmov r3,# 0CMP r0,r1beq on_ddrclean_loop:str r3,[r0], #4cmp r0,r1bne clean_loop//jump On_ddr:ldr pc,=mainhalt:b Halt

Nand.c#include "Tiny6410Addr.h"//nand Flash command # define Nand_cmd_read00#define nand_cmd_read11#define Nand_cmd_ Rndout5#define nand_cmd_pageprog0x10#define nand_cmd_readoob0x50#define nand_cmd_erase10x60#define NAND_CMD_ Status0x70#define nand_cmd_status_multi0x71#define nand_cmd_seqin0x80#define nand_cmd_rndin0x85#define NAND_CMD_ Readid0x90#define nand_cmd_erase20xd0#define nand_cmd_reset0xff/*typedef struct{void (*nand_reset) (void); void (* nand_select_chip) (void), void (*nand_deselect_chip) (void), void (*write_cmd) (int cmd), void (*read_cmd) (int cmd), void ( *wait_idle) (void); void (*WRITE_ADDR) (unsigned int addr); }nand_chip;static nand_chip nand_chip;*/void nand_init (void); Tiny6410 NAND Flash operation function Declaration of static void Tiny6410_nand_reset (void); Restart the static void tiny6410_nand_select_chip (void); Chip select Enable static void Tiny6410_nand_diselect_chip (void);//Turn off the chip select static void tiny6410_write_cmd (int cmd); Write command static void tiny6410_read_cmd (int cmd);  Read command static void Tiny6410_wait_idle (void); Wait for static voidTINY6410_WRITE_ADDR (unsigned int addr); Write address///////////////////////////////////////////tiny6410 NAND Flash operation function Implementation of static void Tiny6410_nand_reset (void) { Tiny6410_nand_select_chip (); Tiny6410_write_cmd (int cmd); Tiny6410_wait_idle (); Tiny6410_nand_diselect_chip ();} Chip select Enable static void Tiny6410_nand_select_chip (void) {Nfcont &= ~ (1 << 1);} Cancels the slice selected static void Tiny6410_nand_diselect_chip (void) {Nfcont |= (1 << 1);} static void tiny6410_write_cmd (int cmd) {}//waits for data static void Tiny6410_wait_idle (void) {do {while (! Nfstat & (1 << 0)); } while (0)}//read command static void tiny6410_read_cmd (int cmd) {nfcmd = cmd;} Write command static void tiny6410_write_cmd (int cmd) {//nfcmd = cmd;} static void Tiny6410_write_addr (unsigned long addr) {nfaddr = 0; nfaddr = 0; Nfaddr = (addr) & 0xFF; nfaddr = (addr >> 8) & 0xFF; nfaddr = (addr >>) & 0xFF;} NAND flash initialization void Init_nand (void) {//SET NAND Flash Controller nfconf = ((0x2 << 12) | (0xf << 8) | (0x7 << 4)); Nfcont |= ((0x3 << 0));} Read to page data static int nand_read_page (unsigned char *buf,unsigned long addr) {int i;//emit the slice-select tiny6410_nand_select_chip ();// Send Read command Tiny6410_read_cmd (NAND_CMD_READ0);//Send address tiny6410_write_addr (addr);//Send Read command Tiny6410_read_cmd (nand_cmd_ Readstart);//wait for Data tiny6410_wait_idle ();//Read 2048 bytes for (i=0; i < page_size; i++) {*buf++ = Nfdata8_reg;} Cancel the tiny6410_nand_diselect_chip (); return 0;} Copy from NAND to Dramint copy2dram (unsigned int nand_start,unsigned int dram_start,unsigned int len) {unsigned char *buf = (unsi gned char *) ddr_start;int i;unsigned int page_shift = 11;//send slice select Tiny6410_nand_select_chip ();//Make Len 2048 an integer times len = (len/ 2048+1) *2048;//cyclic copy, one page per copy of data for (i = 0; i < (len>>page_shift); i++, buf+= (1<<page_shift)) {//read one page, namely 2048bytenandll_read_page (buf, i);} return 0;}

nand.ldssections {    . = 0x50000000;    . Text: {start.oclock.osdram.onand.o* (. Text)}.rodata: {* (. rodata)}.data: {* (. data)}    Bss_start =.;    . BSS ALIGN (4)  : {* (. BSS)  * (COMMON)}    bss_end =.;}

Tinyaddr.h#ifndef _tiny6410addr_h#define _TINY6410ADDR_H//GPK #define GPKIO_BASE (0x7f008800) #define RGPKCON0 (* ( Volatile unsigned long *) (gpkio_base+0x00)) #define RGPKDAT (* (volatile unsigned long *) (gpkio_base+0x08))//clock# Define Apll_lock (* (volatile unsigned long *) 0x7e00f000) #define Mpll_lock (* ((volatile unsigned long) 0x7e00f004) # Define Epll_lock (* (volatile unsigned long *) 0x7e00f008) #define OTHERS (* ((volatile unsigned long *) 0x7e00f900) #defi Ne clk_div0 (* (volatile unsigned long *) 0x7e00f020) #define APLL_CON (* ((volatile unsigned long) 0x7e00f00c) #define M Pll_con (* (volatile unsigned long *) 0x7e00f010) #define CLK_SRC (* ((volatile unsigned long *) 0x7e00f01c) Efine ULCON0 (* (volatile unsigned long *) 0x7f005000) #define UCON0 (* ((volatile unsigned long *) 0x7f005004) #def Ine UFCON0 (* (volatile unsigned long *) 0x7f005008) #define UMCON0 (* ((volatile unsigned long *) 0x7f00500c) #defin E UTRSTAT0 (* (volatile unsigned long *) 0x7f005010)) #define UFSTAT0 (* (volatile unsigned long *) 0x7f005018) #define UTXH0 (* (Volatile unsigned char * )) #define URXH0 (* (volatile unsigned char *) 0x7f005024) #define UBRDIV0 (* (volatile unsigned short *) (0x7f005020) 0x7f005028)) #define UDIVSLOT0 (* (volatile unsigned short *) 0x7f00502c) #define GPACON (* (volatile unsigned long *) 0 x7f008000))//sdram#define p1memstat (* ((volatile unsigned long) 0x7e001000) #define P1MEMCCMD (* (Volatile unsigned long *) 0x7e001004)) #define P1DIRECTCMD (* (volatile unsigned long *) 0x7e001008)//#define MEMCCMD (* (Volatile unsigned long *) 0x7e001004) #define P1REFRESH (* (volatile unsigned long *) 0x7e001010) #define P1CASLAT (* (Volatile unsigned long *) 0x7e001014) #define MEM_SYS_CFG (* (volatile unsigned long *) 0x7e00f120) #define P1MEMCFG (* (Volatile unsigned long *) 0x7e00100c) #define P1T_DQSS (* (volatile unsigned long *) 0x7e001018) #define P1T_MRD (* (Volatile unsigned long * 0x7e00101c)) #define P1T_RAS (* (Volatile unsignedlong *) 0x7e001020) #define P1T_RC (* (volatile unsigned long *) 0x7e001024) #define P1T_RCD (* (volatile unsigned long *) 0x7e001028)) #define P1T_RFC (* (volatile unsigned long *) 0x7e00102c) #define P1T_RP (* (volatile unsigned long *) 0x7e001030)) #define P1T_RRD (* (volatile unsigned long *) 0x7e001034) #define P1T_WR (* (volatile unsigned long *) 0x7e001038)) #define P1T_WTR (* (volatile unsigned long *) 0x7e00103c) #define P1T_XP (* (volatile unsigned long *) 0x7e001040)) #define P1T_XSR (* (volatile unsigned long *) 0x7e001044) #define P1T_ESR (* (volatile unsigned long *) 0x7e001048)) #define P1MEMCFG2 (* (volatile unsigned long *) 0x7e00104c) #define P1_CHIP_0_CFG (* (volatile unsigned long *) 0x7e001200))//nand#define nand_base (0x70200000) #define NFCONF (* ((volatile unsigned long *) Nand_base + 0x00) #def Ine Nfcont (* (volatile unsigned long *) Nand_base + 0x04) #define NFCMMD (* (volatile unsigned long *) nand_base + 0x08)) #define NFADDR (* ((volatile unsigned long *) Nand_base + 0x0c))#define NFDATA (* (volatile unsigned long *) Nand_base + 0x10) #define NFMECCDATA0 (* (volatile unsigned long *) NA Nd_base + 0x14)) #define NFMECCDATA1 (* (volatile unsigned long *) Nand_base + 0x18) #define NFSECCDATA0 (* (volatil      e unsigned long *) Nand_base + 0x1c)) #define NFSBLK (* ((volatile unsigned long *) Nand_base + 0x20) #define Nfeblk  (* (volatile unsigned long *) Nand_base + 0x24)) #define NFSTAT ((volatile unsigned long *) Nand_base + 0x28) #define  NFESTAT0 (* (volatile unsigned long *) Nand_base + 0x2c) #define NFESTAT1 (* (volatile unsigned long *) nand_base + 030)) #define NFMECC0 (* (volatile unsigned long *) Nand_base + 0x34) #define NFMECC1 (* (Volatile unsigned lon G *) Nand_base + 0x38)) #define NFSECC (* (volatile unsigned long * nand_base + 0x3c)) #define NFMLCBITPT (* (Volat Ile unsigned long *) Nand_base + 0x40)//* #define NF8ECCERR0 (* ((volatile unsigned long *) Nand_base + 0x44) #define N F8ECCERR1 (* (VolatIle unsigned long *) Nand_base + 0x48) #define NF8ECCERR2 (* ((volatile unsigned long *) Nand_base + 0x4c) #define NFM 8ECC0 (* (volatile unsigned long *) Nand_base + 0x50) #define NFM8ECC1 (* (volatile unsigned long *) Nand_base + 0x54)) #define NFM8ECC2 (* (volatile unsigned long *) Nand_base + 0x58) #define NFM8ECC3 (* (volatile unsigned L Ong *) Nand_base + 0x5c)) #define NFMLC8BITPT0 (* ((volatile unsigned long *) Nand_base + 0x60) #define NFMLC8BITPT1 ( * (volatile unsigned long *) Nand_base + 0x64) */#endif

Summarize:

The summary is divided into two major strides.

The first step: Read the s3c6410 data sheet to understand the Nandflash operation process.

Step two: Read the NAND flash data sheet to find out the specific settings for each register.

　　

Tiny6410 NAND flash Drive