Usage of several equal signs in makefile

There are four ways to assign values to variables in make:

1.: = operator, such as make_depend: = $ (CC)-m
This method is called "simple expansion", because the right side of the equals sign is expanded immediately when this line in makefile is read, and all variables referenced on the right side of the equals sign (such as cc In the example) it will be expanded immediately. Its behavior is the same as that in general programming and scripting languages.
When the variable referenced on the right of the equal sign (such as cc In the example) is not defined, it is expanded into a null (nothing) instead of a space.
2. = operator, such as make_depend = $ (CC)-m
This method is called "recursive expansion". The content on the right of the equal sign is not expanded until the variable is used. In fact, it is more appropriate to call it "delayed expansion. The magic is that variables can be defined in no order in this expansion mode. For example:
Make_depend = $ (CC)-m
...
# Some time later
Cc = gcc
As long as make_depend has not been referenced before.

In addition, it is not just "delayed expansion". In fact, the content on the right of the equal sign is re-expanded every time this variable is used.
3 .? = Operator, such as output_dir? = $ (Project_dir)/out
This method is called "Conditional expansion". Values are assigned only when output_dir is not defined. Otherwise, nothing is done. This method is particularly useful in processing environment variables.

4. + = operator, such as output_dir + = $ (project_dir)/out
Append. The main purpose is to Append content to the variable "recursive expansion. Simple variables can be appended with the simple: = $ (simple) New stuff method. For recursive expansion variables, recursive = $ (recursive) New stuff will cause loop reference. In this case, only the + = operator can be used.

 

This article from the csdn blog, reproduced please indicate the source: http://blog.csdn.net/lgxqf/archive/2007/10/31/1859685.aspx