Use of timequest static time series analysis learning notes Tool

Chapter 3 Use of tools

Here I will explain the simple use of the timequest tool through several constraints commands.

3.1 creat_clock constraint command

Related code:

 

Figure 27

Step 1: Find the timequest timing analyze option in the tools us II Tools menu and open it. The 27 session box appears:

 

Figure 28

Report window: through this window, we can know what tasks timequest has performed.

Task window: This window enables timequest to execute the tasks you require. For example, if you click report clocks, timequest will constrain the clock in the information display window.

Console: You can enter the Tcl command for timequest to execute the corresponding task.

Information display window: timequest displays the result information of the current task in this window.

Step 2: Click create_timing_netlist In the taskbar or the create_timing_netlist option in the netlist drop-down menu of the main menu. If you select this option, the following dialog box appears:

 

Figure 29

First, we can see that the leftmost input netlist can be post-fit or post-map. The post-fit is closer to the physical result (with optimization), and the post-map is closer to the prototype (without optimization ). The delay model on the right is divided into slow-corner and fast-corner, and slow refers to the worst case of timequest analysis, such as the model where FPGA works in poor environments, fast refers to a situation in which timequest analyzes FPGA in a normal environment and is closer to reality. Zero IC delays ignores the latency of some basic network labels.

We usually choose post-fit and slow-corner combinations. In this case, if the design meets the timing requirements, our design will be more reliable. In fact, the create_timing_netlist in the task window is the default combination, so we can click this option.

Step 3: after creating a network table, create the first constraint command.

 

Figure 30

The input clock CLK is restricted here. The clock period is 40ns and the clock name is CLK. After you click Run, find the write SDC file option in the constrants drop-down menu of the main menu and click Generate the name t1.out. SDC file.

Step 4: add the SDC file. Click the setting option in the assignments drop-down menu of the main menu in Quartus II to bring up the 29 session box. Find the timequest timing analyze option in the session box and add the SDC file.

 

Figure 31

Step 5: double-click the report clocks in the timequest Timing Analyzer task window. Then, in the information display box, you can see the clock we just constrained, 31:

 

Figure 32

There are several ways to generate SDC files, which I prefer.

In the second chapter, it is said that creat_clock can also constrain virtual clocks. These clocks are not used internally in FPGA. They are external IC clocks and must be used in I/O constraints. Because the SDC file has been generated before, it will be added later through the insert cronstrain option in the edit option drop-down menu of the Quartus II software main menu when adding the constraint command, in this way, the command will be directly added to the SDC file. After each command is added, if you want to analyze it in timequest Timing Analyzer, you must load the SDC file again. Double-click reset design, read SDC file, and update timing netlist.

 

Figure 33

Create a virtual clock using creat_clock. Here I have created two virtual time series: ext1_clk and ext2_clk. View the changes in the SDC file and timequest Timing Analyzer information display box, 34:

 

Figure 34

In the column "type", the types of ext1_clk and ext2_clk are virtual.

 

 

3.2 creat_generated_clock

The Code shows that the clock here contains the first, second, and fourth articles about the effect of the creat_generated_clock constraint command. sys_clk corresponds to 1st articles, and ext_div2 corresponds to 4th articles, ext_clk1 and ext_clk2 correspond to 2nd entries. Then we use the creat_generated_clock session box to constrain the three types, 35:

Constraint commands for SDC files

 

Figure 35

36. Double-click report clocks in the task window and observe the window clock information. Here, we can see the cycle, frequency, type, and source clock of each restricted clock.

 

Figure 36

37. Double-click report timing in the task window and observe the clock condition in the window. Here we can see the paths analyzed by timequest, the paths from input DIN to rdata1 and rdata2 to output dout are not analyzed because timequest analyzes the paths between two registers rather than the paths from the analysis registers to the pins, FPGA pins are dealing with external IC, so here we need to add the set input delay and set output delay constraints so that timequest can analyze these paths.

 

Figure 37

Now let's take a look at which clocks are constrained by these commands:

Constraint PLL, corresponding to sys_clk: derive_pll_clocks

Constraint ext_div2: create_generated_clock-name ext_div2-source [get_pins {pll0_m1 | altpll_component | PLL | CLK [0]}]-divide_by 2 [get_keepers {ext_div2}]

Constraints: ext_clk1 and ext_clk2: create_generated_clock-name ext_clk1-source [get_keepers {ext_div2}] [get_ports {ext_clk1}]

Create_generated_clock-name ext_clk2-source [get_keepers {ext_div2}] [get_keepers {ext_div2}]

Conclusion 3.3

Summary, which is very clear above.

Use of timequest static time series analysis learning notes Tool