Verilog Learning Notes Simple function realization (vi) ....... Counting divider Circuit

The most important concepts in the divider circuit are two; 1) odd-divided/even-divided; 2) duty-free.

A) The simplest of these is the two-way circuit, the duty ratio is 50%, its Verilog program is

1 ModuleHALF_CLK (CLR,CLK_IN,CLK_OUT,OUT2);2   inputclr,clk_in;3   OutputClk_out,out2;4   RegClk_out,out2;5   6    always@(Posedgeclk_in)7   begin8   if(clr==0)beginclk_out=0; Out2=1;End9     Else beginclk_out<=~clk_out; Out2=~out2;EndTen   End One Endmodule 

The waveform diagram looks like this:

B) using counter to achieve the count divider (even) duty ratio of 50%, such as the implementation of 40, the program is as follows:

1 Modulefdivision (rst,clkin,clkout);2   inputRst,clkin;3   Outputclkout;4   Regclkout;5   Reg[4:0]i;6    always@(PosedgeClkin)7   begin8   if(!rst)beginclkout<=0; i<=0;End9     Else beginTen          if(i== +) One            beginclkout<=~clkout;i<=0;End A            Else -i<=i+1; -          End the   End - Endmodule 

Waveform diagram:

C) to achieve the singular frequency division, and the duty ratio adjustable divider, such as 5, the duty ratio is 50%,40%

1 Modulefdivision5 (clkin,clkout);2   inputClkin;3   Outputclkout;4    Wireclkout;5   Reg[2:0]step,step1;6    always@(PosedgeClkin)7   begin8      Case(STEP)9       3'b000:step<=3'b010;Ten       3'b010:step<=3'B100; One       3'b100:step<=3'b001; A       3'b001:step<=3'b011; -       3'b011:step<=3'b000; -       defaultstep<=3'b000; the     Endcase -   End -    always@(NegedgeClkin) -   begin +    Case(STEP1) -       3'b000:step1<=3'b010; +       3'b010:step1<=3'B100; A       3'b100:step1<=3'b001; at       3'b001:step1<=3'b011; -       3'b011:step1<=3'b000; -       defaultstep1<=3'b000; -     Endcase -   End -   AssignClkout= (step[0]|step1[0]); in Endmodule

Top-level file (testbench):

1' Timescale 1ns/1ns2' Define Half_period -3 Modulefdivision5_test;4   RegClkin;5    Wireclkout;6    WireStep,step1;7   Initial8   begin9clkin=0;Ten   End One    always# ' Half_period clkin=~Clkin; A fdivision5 m (clkin,clkout); -   Assignstep=M.step; -   Assignstep1=M.step1; the Endmodule

Waveform diagram:

Verilog Learning Notes Simple function realization (vi) ....... Counting divider Circuit