What does DFT mean?

 

DFT: Introduction to digital circuit (FPGA/ASIC) design-testability design and analysis, discrete Fourier transformation, (DFT) Direct fouriet Transformer

Design for testability-DFT is an attempt to increase the controllability and Observability of the signal in the circuit, so as to timely and economically test whether the chip has physical defects, enable users to obtain good chips. These include ad hoc technology and structured design technology. Currently, any high-ICPs adopt structured design technologies, including scanning and built-in self-testing.

The testing of a circuit involves two aspects:
The level value of each node in the circuit is controlled by an external input signal.
It is called observability to observe the difficulty of internal faults from the external output end.

Scanning technology refers to the ability to move in or out any State in a circuit, and its characteristics make the test data serialized. Full scan and boundary scan are commonly used. The full scan technology replaces all the triggers in the circuit with the specially designed trigger with scan function, so that they are linked to one or several shift registers during testing, the circuit is divided into pure combo circuits and shift registers that can be tested separately. All States in the circuit can be controlled and observed directly from the original input and output. This circuit simplifies the Test Generation of the time series circuit into the Test Generation of the combination circuit.AlgorithmAt present, it has been relatively complete, and it is much easier to generate test automation than the Test Generation of time series circuit, thus greatly reducing the difficulty of Test Generation.

Generally, the manufacturer provides a dedicated BIST circuit for testing the memory module. The BIST circuit can be used to conveniently test the access function of the storage unit, the so-called BIST circuit refers to the implementation of the test circuit into the IC, and the use of the inherent capabilities of the test circuit to self-execute a test memoryProgram. In addition, mbist can solve the ram shadow problem and improve the testability of the chip.

Why is DFT required? Because our design, that is, the layout from RTL to gdⅱ, is just a layout. At last, the chips need to be produced and woven in foundry, that is, the manufacturers make the Chips Based on the data you provide. This process may contain defects, which may be physical or legacy issues in the design. On the other hand, defects may also occur in the encapsulation process. To ensure that our chips do not have physical defects, We Need To Do DFT. That is to say, if you give foundry the gdⅱ of a sub-device, defects may be introduced during the process and encapsulation. How do you know when you get this sub-device chip, what the manufacturer has done for you is a normal job and door? How do you know that the dier of the generator made by the manufacturer can be normally input by the pins after encapsulation? In a word, it is through DFT!