What makes an inferred latch?
For combinatorial logic, the output of the circuit are a function of input only and should not contain any memory or intern Al State (latch).
In Verilog, a variable would keep its previous value if it's not assigned a value of an always block. A latch must is created to store this present value.
An incomplete If-else statement would generate latches. An if-else statement was considered "incomplete" if the output state was not a defined for all possible input conditions. The same goes for an incomplete case statement, or a case statement that does does have a default:item.
Why is inferred latches bad?
Inferred latches can serve as a ' warning sign ', the logic design might not being implemented as intended. A crucial If-else or case statement might is missing from the design.
Latches can leads to timing issues and race conditions. They may leads to combinatorial feedback-routing of the output back to the Input-which can be unpredictable.
To avoid creating inferred latches:
Include all the branches of a if or case statement
Assign a value to every output signal in every branch
Use default assignments at the start of the procedure, so every signal would be assigned.
Some parts paraphrased from ' FPGA prototyping by Verilog Examples ' by P. Chu
When does know you need latches?
Which, as you implied, is a subjective question. Expect more opinion than fact as answers. That being said, this is my opinion:
I, like your, often find better ways to use flip-flops thus avoiding latches. The resulting logic is often more elegant and robust. But there is times where I I don ' t have enough control over the logic to avoid latches. For example, I might is interfacing to a processor bus that requires latches to meet the desired specifications. Since I can ' t redesign the CPU or the bus, I ' m stuck with the latch.
In the past 13+ years, that's the only time I had needed latches.
What makes an inferred latch? How to avoid creating inferred latches? When does know you need latches?