Arm history introduction

 

The ARM processor architecture provides support for the 32-bit ARM and 16-bit Thumb
Instruction Set Architectures (ISAs) along with architecture extensions
to provide support for Java acceleration (Jazelle), security (TrustZone), Intelligent Energy Manager (IEM), SIMD, and NEONTM technologies.

The
ARM ISA is constantly improving to meet the increasing demands of
leading edge applications developers, while retaining the backwards
compatibility necessary to protect investment in software development.

ARMv4
The
oldest version of the processor architecture supported today. All
previous versions are now obsolete. Implementations include some
members of the ARM7 processor family and Intel StrongARM processors. ARMv4 can be considered a 32-bit ISA operating in a 32-bit address space.

ARMv4T
The ARMv4T processor architecture added the 16-bit Thumb instruction
set which enabled compilers to generate more compact code (memory
savings of up to 35% over the equivalent 32-bit code), while retaining
all the benefits of a 32-bit system.

ARMv5TE
In 1999, the ARMv5TE processor architecture introduced improvements to the Thumb architecture, along with ARM ‘Enhanced’ DSP (digital signal processing) instruction set extensions to the ARM ISA.

The
Thumb changes added a few new instructions along with improvements to
Thumb/ARM interworking, greatly improving compiler capabilities and the
ability to mix and match ARM versus Thumb routines to balance code size
and performance.

The enhanced DSP instructions include support
for saturated arithmetic, and provide up to 70% performance improvement
for audio DSP applications. Many systems require the flexibility of a
microcontroller combined with the data-processing capability of a DSP,
historically forcing designers to compromise performance with cost, or
adopt complex multi processor strategies. The ‘E’ instruction set
extensions were designed to provide a DSP capability in a general
purpose CPU, resulting in improved performance and flexibility.

ARMv5TEJ
In
2000, the ARMv5TEJ processor architecture added the Jazelle technology
extension to support Java acceleration technology, which is
particularly suited to small memory footprint designs. Jazelle
technology’s acceleration of Java bytecodes provides significantly
higher performance than a software-only based Java Virtual Machine
(JVM), accelerating Java execution by 8x and providing an 80% reduction
in power consumption compared to a non Java-accelerated core. This
functionality gives platform developers increased freedom to run Java
code alongside established operating systems (OS) and applications on
an ARM processor.

ARMv6
The
ARMv6 processor architecture, announced in 2001, features improvements
in many areas covering the memory system, improved exception handling
and better support for multiprocessing environments. ARMv6 also
includes media instructions to support Single Instruction Multiple Data (SIMD)
software execution. The SIMD extensions are optimized for a broad range
of software applications including video and audio codecs, where the
extensions increase performance by up to four times. In addition
Thumb-2 and TrustZone technologies were introduced as variants of the
ARMv6 architecture. The first implementation of the ARMv6 architecture was the ARM1136J(F)-STM processor announced in Spring 2002, followed by the ARM1156T2(F)-STM and the ARM1176JZ(F)-STM processors in 2003.

ARMv7
The ARMv7 processor architecture lies below the CortexTM family of processors and defines three distinct processor profiles: the A profile for sophisticated, virtual memory-based OS
and user applications; the R profile for real-time systems; and the M
profile optimized for microcontroller and low-cost applications.

All ARMv7 architecture profiles implement Thumb -2 technology
which is built on the foundation of the ARM industry-leading Thumb code
compression technology, while retaining complete code compatibility
with existing ARM solutions. The ARMv7 architecture also includes the NEON technology
extensions to increase DSP and media processing throughput by up to 400
percent, and offers improved floating point support to address the
needs of next generation 3D graphics and games physics, as well as
traditional embedded control applications.

NEON Media Acceleration Technology
ARM NEON technology
is an architecture option with the ARMv7A architecture and is designed
to address the demands of next generation high-performance, media
intense, low power mobile handheld devices. NEON technology is a
64/128-bit hybrid SIMD architecture, developed by ARM to accelerate the
performance of multimedia and signal processing applications including
video encode/decode, 3D graphics, speech processing, compressed audio
decoding, image processing, telephony and sound synthesis.

Vector Floating Point (VFP)
Vector
Floating Point (VFP) coprocessor support is an architecture option. The
VFP architecture supports single and double precision floating point
arithmetic, and is fully IEEE 754 compliant with suitable software
library support. The VFP architecture also includes a fully
deterministic ‘Run fast Mode’.

Provision of a
hardware floating point is essential for many applications, and can be
used as part of a System on Chip (SoC) design flow using technical
computing tools (eg MatLab and MATRIXx) to directly model the system
and derive the application code. The vector processing capability of
the ARM VFP can be used to increase performance of imaging applications
such as scaling, 2D and 3D transforms, font generation, and digital
filters.

ARM currently has VFP support for the ARM9, ARM10 and ARM11 processor families: VFP9-S and VFP10. Additional VFP options, VFPv3, were introduced with the ARMv7 architecture.

ARM TrustZone
The ARM TrustZone extensions
provide hardware support for two separate address spaces, such that
code executing in the non-secure world cannot gain access to any
address space marked as secure. A new monitor mode supports transition
between the two worlds.
 
The technology provides a secure
environment for system features such as key management and/or
authentication mechanisms enabled by an open OS. The protection
provided by the technology is necessary for consumer privacy and
extending a range of services, such as mobile banking and multimedia
entertainment, to widespread consumer adoption and use.

Thumb-2 Technology
ARM and Thumb code each execute in their own processor state. Thumb-2 core
technology adds a mixed mode capability, defining a new set of 32-bit
instructions that execute alongside traditional 16-bit instructions in
Thumb state. This reduces, or can remove, the need for balancing ARM
and Thumb code in a system, providing ‘ARM levels of performance’ with
‘Thumb code density’.

Thumb-2 technology
builds on the success of Thumb technology, adding to ARM’s strengths as
the leading supplier of low power, high performance processors and
systems, supply cost effective and timely solutions across a wide range
of market segments.

Other Related Technologies
In
addition to the above technologies, several other system technologies
with their own architecture provisions are available from ARM.

Debug and Trace 
ARM's
debug and trace tools enable system developers to quickly debug
real-time software, and to trace instruction execution and associated
program data at full core speed. The debug and trace offering includes
host based tools along with components such as EmbeddedICE, Embedded Trace Macrocell (ETM), and the latest CoreSight technology, which form part of a modern SoC.

AMBA
The
AMBA protocol is an open standard, on-chip bus specification that
details a strategy for the interconnection and management of functional
blocks that makes up a System-on-Chip (SoC). It facilitates
"right-first-time" development of embedded processors with one or more
CPU/signal processors and multiple peripherals. The AMBA protocol
enhances a reusable design methodology by defining a common backbone
for SoC modules. 

ARM Intelligent Energy Manager
ARM Intelligent Energy Manager (IEMTM)
technology implements advanced algorithms to optimally balance
processor workload and energy consumption, while maximizing system
responsiveness to meet end-user performance expectations. The
Intelligent Energy Manager technology works with the OS and
applications running on the mobile phone to dynamically adjust the
required CPU performance level through a standard programmer's model.