BCD碼編碼器_逐步移位法

September 14, 2016
作者：dengshuai_super
出處：http://blog.csdn.net/dengshuai_super/article/details/52541402
聲明：轉載請註明作者及出處。

BCD碼編碼器（Binary-BCD Converter）_逐步移位法

逐步左移，當BCD0移成11時等於3<4,不用作調整；
當BCD0移成111時等於7>4，加3等於10，對應的二進位為1010；
再次移位後，BCD1為1，BCD0為0101等於5>4,加3後等於8對應的二進位為1000；
再次移位，BCD1=11，BCD0=0001，bin=11，因為BCD1和BCD0都<4,因此不用操作；
再次移位，BCD1=110，BCD0=0011，bin=1，因為BCD1=6>4，加3後等於9，對應二進位為1001，此時BCD1=1001，BCD0=0011，bin=1；
最後一次移位：BCD2=1，BCD1=0010，BCD0=0111。

module binary_to_bcd (  clk_i,  ce_i,  rst_i,  start_i,  dat_binary_i,  dat_bcd_o,  done_o  );parameter BITS_IN_PP         = 16; // # of bits of binary inputparameter BCD_DIGITS_OUT_PP  = 5;  // # of digits of BCD outputparameter BIT_COUNT_WIDTH_PP = 4;  // Width of bit counter// I/O declarationsinput  clk_i;                      // clock signalinput  ce_i;                       // clock enable inputinput  rst_i;                      // synchronous resetinput  start_i;                    // initiates a conversioninput  [BITS_IN_PP-1:0] dat_binary_i;        // input busoutput [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;  // output busoutput done_o;                     // indicates conversion is donereg [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;// Internal signal declarationsreg  [BITS_IN_PP-1:0] bin_reg;reg  [4*BCD_DIGITS_OUT_PP-1:0] bcd_reg;wire [BITS_IN_PP-1:0] bin_next;reg  [4*BCD_DIGITS_OUT_PP-1:0] bcd_next;reg  busy_bit;reg  [BIT_COUNT_WIDTH_PP-1:0] bit_count;wire bit_count_done;//--------------------------------------------------------------------------// Functions & Tasks//--------------------------------------------------------------------------function [4*BCD_DIGITS_OUT_PP-1:0] bcd_asl;  input [4*BCD_DIGITS_OUT_PP-1:0] din;  input newbit;  integer k;  reg cin;  reg [3:0] digit;  reg [3:0] digit_less;  begin    cin = newbit;    for (k=0; k<BCD_DIGITS_OUT_PP; k=k+1)    begin      digit[3] = din[4*k+3];      digit[2] = din[4*k+2];      digit[1] = din[4*k+1];      digit[0] = din[4*k];      digit_less = digit - 5;      if (digit > 4'b0100)      begin        bcd_asl[4*k+3] = digit_less[2];        bcd_asl[4*k+2] = digit_less[1];        bcd_asl[4*k+1] = digit_less[0];        bcd_asl[4*k+0] = cin;        cin = 1'b1;      end      else      begin        bcd_asl[4*k+3] = digit[2];        bcd_asl[4*k+2] = digit[1];        bcd_asl[4*k+1] = digit[0];        bcd_asl[4*k+0] = cin;        cin = 1'b0;      end    end // end of for loop  endendfunction//--------------------------------------------------------------------------// Module code//--------------------------------------------------------------------------// Perform proper shifting, binary ASL and BCD ASLassign bin_next = {bin_reg,1'b0};always @(bcd_reg or bin_reg)begin  bcd_next <= bcd_asl(bcd_reg,bin_reg[BITS_IN_PP-1]);end// Busy bit, input and output registersalways @(posedge clk_i)begin  if (rst_i)  begin    busy_bit <= 0;  // Synchronous reset    dat_bcd_o <= 0;  end  else if (start_i && ~busy_bit)  begin    busy_bit <= 1;    bin_reg <= dat_binary_i;    bcd_reg <= 0;  end  else if (busy_bit && ce_i && bit_count_done && ~start_i)  begin    busy_bit <= 0;    dat_bcd_o <= bcd_next;  end  else if (busy_bit && ce_i && ~bit_count_done)  begin    bcd_reg <= bcd_next;    bin_reg <= bin_next;  endendassign done_o = ~busy_bit;// Bit counteralways @(posedge clk_i)begin  if (~busy_bit) bit_count <= 0;  else if (ce_i && ~bit_count_done) bit_count <= bit_count + 1;endassign bit_count_done = (bit_count == (BITS_IN_PP-1));endmodule

來源：
https://ke.qq.com/user/tasks/index.html?cid=117307#tid=100127911&fr=2