Bootloader源碼

include "def.h"
#include "2440addr.h"
#include "2440lib.h"

#define puts Uart_Printf
#define printf Uart_Printf
#define getch Uart_Getch

#ifndef DEBUG_VERSION
#define USE_UART_INT
#endif

extern U32 downloadAddress, downloadFileSize;
static U8 *temp;

#ifdef USE_UART_INT
static void __irq Uart0RxInt(void)
{
    ClearSubPending(BIT_SUB_RXD0); //rSUBSRCPND = BIT_SUB_RXD0;          //Clear pending bit (Requested)
    ClearPending(BIT_UART0);

    *temp ++= RdURXH0();
}

static void __irq Uart1RxInt(void)
{
    ClearSubPending(BIT_SUB_RXD1); //rSUBSRCPND = BIT_SUB_RXD1;          //Clear pending bit (Requested)
    ClearPending(BIT_UART1);

    *temp ++= RdURXH1();
}
#endif

void call_linux(U32 a0, U32 a1, U32 a2);

void comdownload(void)
{
 U32 size;
 U8 *buf;
 U16 checksum;
 int up;
 
 puts("/nNow download file from uart0.../n");
 downloadAddress = _NONCACHE_STARTADDRESS;
 buf  = (U8 *)downloadAddress;
 temp = buf-4;
 
 Uart_GetKey();

#ifdef USE_UART_INT
 up = Uart_Select(-1);      //get the console port
 if(!up) {
  pISR_UART0 = (U32)Uart0RxInt;  //串口接收資料中斷
  ClearSubPending(BIT_SUB_RXD0);
  ClearPending(BIT_UART0);
  EnableSubIrq(BIT_SUB_RXD0);
  EnableIrq(BIT_UART0);
 } else {
  pISR_UART1 = (U32)Uart1RxInt;  //串口接收資料中斷
  ClearSubPending(BIT_SUB_RXD1);
  ClearPending(BIT_UART1);
  EnableSubIrq(BIT_SUB_RXD1);
  EnableIrq(BIT_UART1);
 }
#endif

 while((U32)temp<(U32)buf)  
    {
 #ifdef USE_UART_INT
        Led_Display(0);
        Delay(1000);
        Led_Display(15);
        Delay(1000);
#else
  *temp++ = Uart_Getch();
#endif
    }       //接收檔案長度,4 bytes 
 
 size  = *(U32 *)(buf-4);
 downloadFileSize = size-6;

#ifdef USE_UART_INT
    printf("Download File Size = %d/n", size);
#endif
 
 while(((U32)temp-(U32)buf)<(size-4))
 {
#ifdef USE_UART_INT 
  Led_Display(0);
        Delay(1000);
        Led_Display(15);
        Delay(1000);
#else
  *temp++ = Uart_Getch();
#endif  
 }

#ifdef USE_UART_INT
 if(!up) {
  DisableSubIrq(BIT_SUB_RXD0);
  DisableIrq(BIT_UART0);
 } else {
  DisableSubIrq(BIT_SUB_RXD1);
  DisableIrq(BIT_UART1);
 }
#endif

#ifndef USE_UART_INT
 printf("Download File Size = %d/n", size);
#endif
 
 checksum = 0;
 for(size=0; size<downloadFileSize; size++)
  checksum += buf[size];
 if(checksum!=(buf[size]|(buf[size+1]<<8))) {
  puts("Checksum fail!/n");
  return;
 }
 
 puts("Are you sure to run? [y/n]/n");
 while(1)
 {
  U8 key = getch();
  if(key=='n')
   return;
  if(key=='y')
   break; 
 }
 
 call_linux(0, 193, downloadAddress);
}

 

#include "def.h"
#include "option.h"
#include "2440addr.h"
#include "2440lib.h"
#include "2440slib.h"
#include "mmu.h"

void MemoryTest(void)
{
    int i;
    U32 data;
    int memError=0;
    U32 *pt;
   
    //
    // memory test
    //
    //Uart_Printf("Memory Test(%xh-%xh):WR",_RAM_STARTADDRESS,(_ISR_STARTADDRESS&0xfff0000));
    //test sdram from _RAM_STARTADDRESS+2M
 Uart_Printf("Memory Test(%xh-%xh):WR",_RAM_STARTADDRESS+0x00200000,(_ISR_STARTADDRESS&0xffff0000));

    //pt=(U32 *)_RAM_STARTADDRESS;
    pt=(U32 *)(_RAM_STARTADDRESS+0x00200000); 
    while((U32)pt<(_ISR_STARTADDRESS&0xffff0000))
    {
 *pt=(U32)pt;
 pt++;
    }
 
    Uart_Printf("/b/bRD");
    //pt=(U32 *)_RAM_STARTADDRESS;
    pt=(U32 *)(_RAM_STARTADDRESS+0x00200000); 
 
    while((U32)pt<(_ISR_STARTADDRESS&0xffff0000))
    {
 data=*pt;
 if(data!=(U32)pt)
 {
     memError=1;
     Uart_Printf("/b/bFAIL:0x%x=0x%x/n",i,data);
     break;
 }
 pt++;
    }
 
    if(memError==0)Uart_Printf("/b/bO.K./n");
}

**************************************************************
 NAME: profile.c
 DESC: To measuure the USB download speed, the WDT is used.
       To measure up to large time, The WDT interrupt is used.
 HISTORY:
     S3C2400X profile.c is ported for S3C2410X.
 **************************************************************/
#include "def.h"
#include "option.h"
#include "2440addr.h"
#include "2440lib.h"
#include "2440slib.h"

#include <stdarg.h>
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>

static int intCount;

void __irq IsrWatchdog(void);

void Timer_InitEx(void)
{
 intCount=0; 
 pISR_WDT_AC97=(U32)IsrWatchdog;
 ClearPending(BIT_WDT_AC97);
 rSUBSRCPND=BIT_SUB_WDT;
 rINTMSK&=~(BIT_WDT_AC97);
 rINTSUBMSK&=~(BIT_SUB_WDT);
}

void Timer_StartEx(void)
{
 int divider=0;
 rWTCON=((PCLK/1000000-1)<<8)|(0<<3)|(1<<2); // 16us
 rWTDAT=0xffff;
 rWTCNT=0xffff;  

 // 1/16/(65+1),interrupt enable,reset disable,watchdog enable
 rWTCON=((PCLK/1000000-1)<<8)|(0<<3)|(1<<2)|(0<<0)|(1<<5);  
}

 

float Timer_StopEx(void)
{
 int count;
 rWTCON=((PCLK/1000000-1)<<8);
 rINTMSK|=BIT_WDT_AC97;
 rINTSUBMSK|=BIT_SUB_WDT;
 count=(0xffff-rWTCNT)+(intCount*0xffff);
 return ((float)count*(16e-6));
}

void __irq IsrWatchdog(void)
{
  rINTSUBMSK|=BIT_SUB_WDT;
  rSRCPND = BIT_WDT_AC97; //Clear pending bit
  rINTPND = BIT_WDT_AC97;
  rINTPND; //Prevent an double interrupt pending
  rSUBSRCPND=BIT_SUB_WDT;
  intCount++;    
  rINTSUBMSK&=~BIT_SUB_WDT;
}

 

#include "def.h"
#include "option.h"
#include "2440addr.h"
#include "2440lib.h"
#include "2440slib.h"
#include "mmu.h"

// 1) Only the section table is used.
// 2) The cachable/non-cachable area can be changed by MMT_DEFAULT value.
//    The section size is 1MB.

 
extern char __ENTRY[]; 

void MMU_Init(void)
{
    int i,j;
    //========================== IMPORTANT NOTE =========================
    //The current stack and code area can't be re-mapped in this routine.
    //If you want memory map mapped freely, your own sophiscated MMU
    //initialization code is needed.
    //===================================================================

    MMU_DisableDCache();
    MMU_DisableICache();

    //If write-back is used,the DCache should be cleared.
    for(i=0;i<64;i++)
     for(j=0;j<8;j++)
         MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
    MMU_InvalidateICache();
   
    #if 0
    //To complete MMU_Init() fast, Icache may be turned on here.
    MMU_EnableICache();
    #endif
   
    MMU_DisableMMU();
    MMU_InvalidateTLB();

    //MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
    //MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB);  //bank0
    if(rBWSCON&0x6)//nor啟動
     MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_NCNB);   //bank0
    else//nand 啟動
     MMU_SetMTT(0x00000000,0x00001000,(int)__ENTRY,RW_CB);   //bank0
    //MMU_SetMTT(0x04000000,0x07f00000,0,RW_NCNB);     //bank0
    MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_NCNB);  //bank1
    MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
    MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
    //MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
    MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for STRATA Flash
    MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
    MMU_SetMTT(0x30000000,0x30100000,0x30000000,RW_CB);   //bank6-1
    MMU_SetMTT(0x30200000,0x33e00000,0x30200000,RW_NCNB); //bank6-2
    //
    MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB);   //bank6-3
    MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
   
    MMU_SetMTT(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
    MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
    MMU_SetMTT(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
    MMU_SetMTT(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used

   
    MMU_SetTTBase(_MMUTT_STARTADDRESS);
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
     //DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
    MMU_SetProcessId(0x0);
    MMU_EnableAlignFault();
     
    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}   

// attr=RW_CB,RW_CNB,RW_NCNB,RW_FAULT
void ChangeRomCacheStatus(int attr)
{
    int i,j;
    MMU_DisableDCache();
    MMU_DisableICache();
    //If write-back is used,the DCache should be cleared.
    for(i=0;i<64;i++)
     for(j=0;j<8;j++)
         MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
    MMU_InvalidateICache();
    MMU_DisableMMU();
    MMU_InvalidateTLB();
    MMU_SetMTT(0x00000000,0x07f00000,0x00000000,attr); //bank0
    MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,attr); //bank1
    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache();
}

void MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
{
    volatile U32 *pTT;
    volatile int i,nSec;
    pTT=(U32 *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
    nSec=(vaddrEnd>>20)-(vaddrStart>>20);
    for(i=0;i<=nSec;i++)*pTT++=attr |(((paddrStart>>20)+i)<<20);
}