ADI SHARC 學習之PLL

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PLL Block Diagram

 

   

 

    Power Management Registers (PMCTL, PMCTL1)The following sections describe the registers associated with the processors power management

functions.  

    The PMCTL register, shown in Figure A-2 is a 32-bit memory-mapped reg-ister. This register contains bits to control phase lock loop (PLL) mul-

tiplier and divider (both input and output) values, PLL bypass mode, and clock control for enabling peripherals (see Table A-3 on pageA-8). This

register also contains status bits, which keep track of the status of the CLK_CFG pins (RO). The reset value of PMCTL is dependent on the CLK_CFG

pins (bits 5–0 and 17–16).

   The PMCTL1 register, shown in Figure A-3 and described in Table A-4, contains the bits for shutting down the clocks to various peripherals and

selecting one of the three FIR/IIR/FFT accelerators. Writes to this register have an effect latency of two PCLK cycles.

 

 

 

 

 

Bypass Mode
Bypass mode must be used if any runtime VCO clock change is required. Setting the PLLBP bit bypasses the entire PLL circuitry. In bypass mode,

the core runs at CLKIN speed. Once the PLL has settled into the new VCO frequency, (which may take 4096 CLKIN cycles) the PLLBP bit may be

cleared to release the core from bypass mode

note:Only VCO frequency changes require bypass mode, therefore this mode is not intended as a standard operating mode.

 

Clocking Golden Rules
The five rules below should be followed to ensure proper processor operation.
1. After power-up the CLK_CFG pins should not exceed the maximum core speed.
2. Software should guarantee minimum/maximum CCLK speed.
3. Software should guarantee maximum VCO clock speed.
4. Bypass requires 4096 CLKIN cycles.
5. Post-divider changes require 14 CCLK cycles.

ADI SHARC 學習之PLL