VHDL語言編程一個注意點

有一點需要注意，下面以一個狀態機器為例進行說明。

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_signed.all;

entity statem is   port (       

        clk   : in std_logic;    

        rst   : in std_logic;            

        selin : in std_logic;                    

        num   : out std_logic_vector (1 downto 0)                

     );  end statem;

architecture alg of statem is

  Type mystate is (st0,st1,st2,st3);

  signal current_state,next_state : mystate;

  begin  

  sync:process(clk,rst)   

      begin     

      if (rst = '1')then   

                current_state <= st0;     

      elsif (clk'event and clk = '1')then   

                current_state <= next_state;     

       end if;   

   end process sync;

   nex:process(clk,selin)  

          begin  

          if(clk'event and clk = '1') then    

                    case current_state is     when st0 => if(selin = '1') then         

                                                                                           next_state <= st1;        

                                                                                       end if;       

                                                                                       num <= "00";     

                                                                 when st1 => if(selin = '1') then         

                                                                                             next_state <= st2;        

                                                                                       end if;        

                                                                                       num <= "01";    

                                                                when st2 => if(selin = '1') then        

                                                                                               next_state <= st3;        

                                                                                       end if;        

                                                                                       num <= "10";     

                                                                when st3 => if(selin = '1') then         

                                                                                                 next_state <= st0;        

                                                                                       end if;        

                                                                                       num <= "11";    

                         end case;          

                  end if;  

    end process nex;

end alg ;

 

為什麼兩個周期輸出才變換一次？

在第一個clk的上升沿到來前 current_state = st0   next_state = st0

在第一個clk的上升沿到來後 current_state = st0   next_state = st1    輸出是 0

在第二個clk的上升沿到來後 current_state = st1  next_state = st1     輸出是 0

在第三個clk的上升沿到來後 current_state = st1   next_state = st2    輸出是 1

重要的是與c語言的不同之處， 在一個clk到來後進入一個process，其中進行計算的訊號的值始終

都是clk到來前所鎖存的值，而不會因為順序執行而使用計算後的值。