1.3 Makefile Project Management

1. Why Use Makefile

Single-Step Command generation Led.bin

[Email protected] lesson1]# CD.

[Email protected] part1]# mkdir Lesson3

[Email protected] part1]# CD Lesson3

[Email protected] lesson3]# chmod 777./

[[email protected] lesson3]# ls

Led.lds led. S Makefile

[[email protected] lesson3]# arm-linux-gcc-g-C LED. S LED.O

[Email protected] lesson3]# Arm-linux-ld-tled.lds-o led.elf LED.O

[[email protected] lesson3]# ls

Led.elf Led.lds LED.O led. S Makefile

[Email protected] lesson3]# arm-linux-objcopy-o binary led.elf led.bin

[[email protected] lesson3]# ls

Led.bin led.elf Led.lds LED.O led. S Makefile

If there are too many commands, we cannot manually enter too many commands

We need more effective tools.

[[email protected] lesson3]# make clean

RM *.o Led.elf Led.bin

[[email protected] lesson3]# make

Arm-linux-gcc-g-O led.o-c led. S

Arm-linux-ld-tled.lds-o led.elf LED.O

Arm-linux-objcopy-o binary led.elf Led.bin

[[email protected] lesson3]# ls

Led.bin led.elf Led.lds LED.O led. S Makefile

To synthesize a command with a lot of commands.

Make

You need to write your own makefile file to complete the automatic compilation

Makefile file

all:led.o

Arm-linux-ld-tled.lds-o led.elf LED.O

Arm-linux-objcopy-o binary led.elf Led.bin

?

Led.o:led. S

Arm-linux-gcc-g-O led.o-c led. S

?

. Phony:clean

Clean

RM *.o Led.elf Led.bin

Makefile Rules

Target:prerequisites

???? Commad #一个tab

Goal: Reliance

???? Command

led.elf:led.o

Arm-linux-ld-tled.lds-o led.elf LED.O

Pseudo-target: Only commands are not dependent. Phony marking pseudo-targets

Clean

RM *.o Led.elf Led.bin

Arm-linux-gcc-g-O led.o-c led. S

[[email protected] lesson3]# ls

Led.lds LED.O LED. S Makefile

[[email protected] lesson3]# make

Arm-linux-ld-tled.lds-o led.elf LED.O

Arm-linux-objcopy-o binary led.elf Led.bin

?

No parameters default first command after make

Variable

APP1:APP1.O FUNC1.O FUNC2.O

???? GCC app1.o func1.o Func3.o–o App1

APP2:APP2.O FUNC1.O Func2.o–o app2

Using default variables

obj=func1.0 FUNC2.O

APP1:APP1.O $ (obj)

???? GCC app1.o $ (obj) –o App1

APP2:APP2.O $ (obj)

???? GCC app2.o $ (obj) –o app2

Directly using system-defined default variables

$^: On behalf of all dependent files

[email protected]: represents the target

$<: First dependent file

Simplified makefile

all:led.o

Arm-linux-ld-tled.lds-o led.elf $^

Arm-linux-objcopy-o binary led.elf Led.bin

?

Led.o:led. S

ARM-LINUX-GCC-G-o [email protected]-C $^

?

. Phony:clean

Clean

RM *.o Led.elf Led.bin

General rules

Led.o:led. S

ARM-LINUX-GCC-G-o [email protected]-C $^

Main.o:main. S

ARM-LINUX-GCC-G-o [email protected]-C $^

Two rules their orders, the target and the dependent name only the suffix name does not like

%.O:%. S

ARM-LINUX-GCC-G-o [email protected]-C $^

Can replace the above two statements

3. Tips for use

Echo: No print commands required

all:led.o

@arm-linux-ld-tled.lds-o led.elf $^

@arm-linux-objcopy-o binary led.elf led.bin

?

Led.o:led. S

@arm-linux-gcc-g-o [email protected]-C $^

?

. Phony:clean

Clean

RM *.o Led.elf Led.bin

[[email protected] lesson3]# make

[[email protected] lesson3]# ls

Led.bin led.elf Led.lds LED.O led. S Makefile

Makefile file name plus –f option

[Email protected] lesson3]# mv Makefile file

[[email protected] lesson3]# make

Make: * * does not specify the target and cannot find the makefile. Stop it.

[[email protected] lesson3]# make-f file

[[email protected] lesson3]# ls

File Led.bin led.elf led.lds led.o LEDs. S

1.3 Makefile Project Management