ADC081S101 Voltage acquisition based on small feet 595 Digital tube display

RTL structure diagram

Acquisition module collects data using SPI communication Miso method

Module Ad_collect
(
Input Sddata,
Input Rst_n,
Output REG CS,
Output Reg SCLK,
Input CLK,
Output [7:0]seg_data,
Output done
);

reg [7:0]cnt;
Reg[4:0]state;
Reg[7:0]data;
Reg Rdone;

[Email protected] (Posedge CLK or Negedge rst_n) begin
if (cs==0) begin sclk<=!sclk; Cnt<=cnt+1;end
if (!rst_n) begin Cs<=1;state<=0;cnt<=0;sclk<=1;rdone=0;end
Else
Begin
Case (state)
0:if (rst_n==1) Begin Cs<=0;state<=state+1;end
1:if (cnt==8) Begin Data[7]<=sddata;state<=state+1;rdone=0;end
2:if (cnt==10) Begin Data[6]<=sddata;state<=state+1;rdone=0;end
3:if (cnt==12) Begin Data[5]<=sddata;state<=state+1;rdone=0;end
4:if (cnt==14) Begin Data[4]<=sddata;state<=state+1;rdone=0;end
5:if (cnt==16) Begin Data[3]<=sddata;state<=state+1;rdone=0;end
6:if (cnt==18) Begin Data[2]<=sddata;state<=state+1;rdone=0;end
7:if (cnt==20) Begin Data[1]<=sddata;state<=state+1;rdone=0;end
8:if (cnt==22) Begin data[0]<=sddata;; State<=state+1;rdone=0;end
9:if (cnt==32) Begin Cs<=1;state<=state+1;sclk<=0;rdone=1;end
10:begin cnt<=cnt+1;if (cnt==42) Begin Cnt<=0;state<=0;rdone=0;end End
Endcase
End
End
Assign Done=rdone;
Assign Seg_data=rdone?data[7:0]:seg_data;

Endmodule

The output of the 8-bit 255 BCD code corresponds to 3.3V display, with the output of the q[7:0] to multiply 13, to the binary to the BCD module, the last digital control shows the position of the decimal point equivalent to divided by 1000.

This is a 8-bit binary-to-BCD code program with Verilog HDL, which has the advantages of less resources, good portability and convenient expansion.
/********************************************\
FILRST_NME:B_BCD.V Author:Medied.Lee
Description:a 8-bit BINARY-TO-BCD Module
REVISION:2010/11/20 Company:
\********************************************/
Module BIN_BCD (RST_N,BINARY,BCD);
Rst_n is the Enable, binary is the binary number to be converted, BCD is the converted BCD code
Parameter b_size=12;
B_size is the number of bits that the binary number occupies, which can be extended as needed
Input Binary,rst_n;//rst_n high-active, low-voltage
Output BCD;
Wire rst_n;
Wire [b_size-1:0] binary;
reg [b_size-1:0] bin;
reg [b_size+3:0] BCD; The length of the BCD should be modified according to the actual situation
reg [b_size+3:0] result; The length of the result =BCD
[Email protected] (binary or Rst_n)
Begin
bin= binary;
result = 0;
if (Rst_n = = 0)
BCD <= 0;
Else
Begin
Repeat (b_size-1)//Loop calculation with repeat statement
Begin
Result[0] = bin[b_size-1];
if (result[3:0] > 4)
result[3:0]=result[3:0]+ 4 ' D3;
if (result[7:4]> 4)
Result[7:4]=result[7:4]+4 ' D3;
if (result[11:8]>4)
Result[11:8] = Result[11:8]+4 ' D3;
Extensions should be continued with reference to this three if statement
if (result[15:12]>4)
result[15:12]= result[15:12]+ 4 ' D3;
result=result<<1;
bin=bin<<1; End
Result[0]= Bin[b_size-1];
bcd<=result;
End
End
Endmodule

The result of the output is decoded by the digital tube

Module Smg_encoder_module (clk,rst_n,num,smg_data);

Input CLK;
Input rst_n;
input [3:0]num;
Output [7:0]smg_data;

/* Common Cathode digital tube: Select the low level (that is, 0) selected digital tube, each segment selected as high level (i.e. 1 + +) selected each digital segment; */

The code from 0 to F is

Parameter
Seg_num0=8 ' h3f,

Seg_num1=8 ' h06,

Seg_num2=8 ' h5b,

Seg_num3=8 ' h4f,

Seg_num4=8 ' H66,

Seg_num5=8 ' h6d,

Seg_num6=8 ' h7d,

Seg_num7=8 ' h07,

Seg_num8=8 ' h7f,

Seg_num9=8 ' h6f,

Seg_numa=8 ' H77,

Seg_numb=8 ' h7c,

Seg_numc=8 ' H39,

Seg_numd=8 ' h5e,

Seg_nume=8 ' h79,

Seg_numf=8 ' h71;

reg [7:0]smg_data_r;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Smg_data_r <= 8 ' b00000000;
Else
Case (NUM)
4 ' D0:smg_data_r <= SEG_NUM0;
4 ' D1:smg_data_r <= seg_num1;
4 ' D2:smg_data_r <= seg_num2;
4 ' D3:smg_data_r <= seg_num3;
4 ' D4:smg_data_r <= seg_num4;
4 ' D5:smg_data_r <= SEG_NUM5;
4 ' D6:smg_data_r <= seg_num6;
4 ' D7:smg_data_r <= seg_num7;
4 ' D8:smg_data_r <= seg_num8;
4 ' D9:smg_data_r <= seg_num9;

Default:smg_data_r <= 8 ' b00000000;
Endcase
End

Assign Smg_data=smg_data_r;

Endmodule

Finally, the serial data sends the data to 595 output.

Module SEG_CHG
(
input clk_in,//25mhz
input rst_n_in,//active with low
input [7:0] datah_f,
Input [7 : 0] Datal_f,
input [7:0] datah_m,
input [7:0] datal_m,
output reg Rclk_out,//74hc595 RCK
Output reg sclk_out ,//74hc595 SCK
Output reg sdio_out//74hc595 SER
);

parameter clk_div_period=3900;//related with Clk_div ' s frequency
parameter delay_period=10000,//related with Delay time and Refresh frequency
parameter clk_div_pulse_period=25000000;//related with Clk_div_pulse_out ' s Frequency
parameter clk_l=2 ' D0;
Parameter clk_h=2 ' D1;
parameter clk_rising_dege=2 ' D2;
parameter clk_falling_dege=2 ' D3;
parameter idle=3 ' D0;
parameter write=3 ' D1;
parameter delay=3 ' D2;
parameter Low =1 ' B0;
Parameter High =1 ' B1;
//initial for Memory register

REG[24:0] CNT;
Reg CLK_DIV_1HZ;
[Email protected] (Posedge clk_in or Negedge rst_n_in)
Begin
if (!rst_n_in) begin
cnt<=0;
clk_div_1hz<=0;
End Else if (cnt== (clk_div_pulse_period-1)) begin
cnt<=0;
clk_div_1hz<=1;
End ELSE begin
cnt<=cnt+1;
clk_div_1hz<=0;
End
End

Clk_div = Clk_in/clk_div_period
Reg Clk_div;
REG[11:0] clk_cnt=0;
[Email protected] (Posedge clk_in or Negedge rst_n_in) begin
if (!rst_n_in) clk_cnt<=0;
ELSE begin
clk_cnt<=clk_cnt+1;
if (clk_cnt== (clk_div_period-1)) clk_cnt<=0;
if (clk_cnt< (CLK_DIV_PERIOD/2)) clk_div<=0;
else clk_div<=1;
End
End

Divide Clk_div 4 State,
RISING and falling are keeped one cycle of clk_in, like a pulse.
REG[1:0] clk_div_state=clk_l;
[Email protected] (Posedge clk_in or Negedge rst_n_in) begin
if (!rst_n_in) clk_div_state<=clk_l;
else Case (Clk_div_state)
Clk_l:begin
if (clk_div) clk_div_state<=clk_rising_dege;
else clk_div_state<=clk_l;
End
clk_rising_dege:clk_div_state<=clk_h;
Clk_h:begin
if (!clk_div) clk_div_state<=clk_falling_dege;
else clk_div_state<=clk_h;
End
clk_falling_dege:clk_div_state<=clk_l;
Default
Endcase
End

Finite state machine,
Reg Shift_flag = 0;
REG[15:0] Data_reg;
REG[2:0] Data_state=idle;
REG[2:0] Data_state_back;
REG[3:0] data_state_cnt=0;
REG[5:0] shift_cnt=0;
REG[25:0] delay_cnt=0;
[Email protected] (Posedge clk_in or Negedge rst_n_in) begin
if (!rst_n_in) begin
data_state<=idle;
data_state_cnt<=0;
End ELSE begin
Case (Data_state)
Idle:begin
data_state_cnt<=data_state_cnt+1;
Case (DATA_STATE_CNT)
0:begin
Data_reg<={{1 ' b1,datah_f[6:0]}, 8 ' h0e};
data_state<=write;data_state_back<=idle;
End
1:begin
data_reg<={datal_f,8 ' h0d};
data_state<=write;data_state_back<=idle;
End
2:begin
data_reg<={datah_m,8 ' h0b};
data_state<=write;data_state_back<=idle;
End
3:begin
data_reg<={datal_m,8 ' h07};
data_state<=write;data_state_back<=idle;
End
4:begin data_state_cnt<=0; End
Default
Endcase
End
Write:begin
if (!shift_flag) begin
if (Clk_div_state==clk_falling_dege) begin
if (shift_cnt==10) rclk_out<=low;
if (shift_cnt==16) begin
shift_cnt<=0;
rclk_out<=high;
data_state<=data_state_back;
End ELSE begin
sclk_out<=low;
sdio_out<=data_reg[15];
Shift_flag <= 1;
End
End
End ELSE begin
if (Clk_div_state==clk_rising_dege) begin
DATA_REG&LT;={DATA_REG[14:0], data_reg[15]};
shift_cnt<=shift_cnt+1;
sclk_out<=high;
Shift_flag <= 0;
End
End
End
Delay:begin
if (delay_cnt==delay_period) begin
data_state<=idle;
delay_cnt<=0;
End Else delay_cnt<=delay_cnt+1;
End

Default
Endcase
End
End

Endmodule

Pin Assignment

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ADC081S101 Voltage acquisition based on small feet 595 Digital tube display