This article is reproduced from Nidetech blog
Chip-to-uboot start-up process ROM→SPL→UBOOT.IMG introduction ROM code in 335x is the first level of Bootlader. When the MPU is power on, it will automatically execute the code here, complete the partial initialization and boot the second level of the Bootlader, the second level of Bootlader to boot the third level bootader, the TI official for the second and third level of bootlader by Uboot provided. SPL To unify all existing implementations for a secondary program loader (SPL) and-allow simply adding of New implementations this generic SPL framework has been created. With the this framework almost all source files for a board can is reused. No code duplication or symlinking is necessary anymore. 1> Basic ARM initialization 2> UART console initialization 3> clocks an D DPLL Locking (minimal) 4> SDRAM initialization 5> Mux (minimal) 6> Bo Otdevice initialization (based on where we is booting from. Mmc1/mmc2/nand/onenand) 7> bootloading real u-boot from the BootDevice and passing control to it. uboot SPL source code Analysis Makefile analysis Open SPL folder only one makefile visible SPL is multiplexed uboot the original code. Main related code files are u-boot-2011.09-psp04.06.00.03/arch/arm/cpu/armv7 u-boot-2011.09-psp04.06.00.03/arch/arm/lib u-boot-2011.09-psp04.06.00.03/drivers & nbsp Ldscript: = $ (Topdir)/board/$ (boarddir)/u-boot-spl.lds This for link script two, u-boot-spl.lds
| Sram 0x402f0400 |
Sdram 0x80000000 |
|
. BSS |
| . TEXT (ARCH/ARM/CPU/ARMV7/START.O) |
|
| . rodata |
|
| . Data |
|
__start for program start __image_copy_end _end, code parsing __start for program start (Arch/arm/cpu/armv7/start. S) . Globl _start This is the start definition entry point for defining the U-boot, the default entry for the assembler is the start label, and the user can also indicate other entry points in the connection script file with the entry flag: Global is a pseudo-operation of the GNU Arm Assembly, declaring that a symbol can be referenced by another document, which is equivalent to declaring a global variable. GLOBL and. Global are the same. This section is the processor's exception handling vector table. The address range is 0x0000 0000 ~ 0x0000 0020, just 8 instructions. Why is it 8 instructions? Here's a count. First, an arm instruction is 32bit (bit), 0x0000 0020 is converted to decimal 2^5=32b (bytes), and a (b) = 4 * 8 (b) = 4 * 8 * 8 (bit), so just 8 instructions (a byte bytes contains 8 bit bits). The following is an exception vector table that is often encountered in assembler programs. ARM processors typically include resets, undefined directives, SWI, prefetch termination, data termination, IRQ, Fiq, and so on, where the definition of the exception vector in U-boot is as follows: _start: b reset _start marking indicates that the oot program starts here. B is a jump without a return (BL is a jump with a return), meaning the unconditional direct jump to the reset label out of the execution program. B is the simplest branch, and once a b instruction is encountered, the arm processor immediately jumps to the given address, where it continues execution. Note the actual value stored in the branch instruction is an offset from the current R15 value, not an absolute address. Its value is calculated by the assembler, which is the 24 bit signed number, left two bits after the symbol extension to 32 bit, the valid offset is the 26 bit. LDR  PC, _undefIned_instr tion //undefined directives LDR  PC, _software_interrupt // Soft interrupt SWI LDR  PC, _prefetch_abort //pre-fetch termination LDR&N BSP; PC, _data_abort //number of visits terminated LDR  PC, _not_used LDR  PC, _irq //Interrupt request IRQ LDR  PC, _fiq &NB Sp Fast Interrupt FIQ #ifdef config_spl_build //This phase performs the following code _undefined_instruction for SPL:. Word _undefined_instruction _ Software_interrupt:. Word _software_interrupt _prefetch_abort: .word _prefetch_abort _data_abort: .word _data_abort _not_used: word _not_used _irq: .word _IRQ _fiq: .word _fiq _pad: . Word 0x12345678/* now 16*4=64 */#else _undefined_instructIon:. Word undefined_instruction _software_interrupt:. Word software_interrupt _prefetch_abort: .word Prefetch_abort _data_abort: .word data_abort _not_used: . Word not_used _IRQ: .word IRQ _fiq: .word Fiq _pad: .word 0x12345678/* Now 16*4=64 */#endif//Config_spl_build */. Word is the unique pseudo-operator for ARM assembly with the following syntax:. Word {,} ... Function: Inserts a 32-bit data queue. (Same as DCD in Armasm). BALIGNL 16,0xdeadbeef. Align pseudo-action is used to indicate alignment: the current position is aligned by adding padding bytes. The next step is to define the individual segments of the code slightly Rest: (Arch/arm/cpu/armv7/start. S) bl save_boot_params save_boot_params: (arch/arm/cpu/armv7/ti81xx/ Lowlevel_init. S) #ifdef config_spl_build LDR R4, =ti81xx_boot_device & nbsp //ti81xx_boot_device = boot_device_nand /start mode Ldr R5, [R0, #BOOT_DEVICE_OFFSET] and R5, R5, #BOOT_DEVICE_MASK STR R5, [R4] #endif &NB Sp BX  LR Back to reset: (Arch/arm/cpu/armv7/start. S) //Set CPU operating mode Set CPU state type for SVC privileged mode Mrs R0, CPSR BIC r0, R0 , #0x1f Orr R0, R0, #0xd3 MSR cpsr,r0 cpu_init_crit: (Arch/arm/cpu/armv7/start. S) mov r0, #0 @ set up for MCR MCR p15, 0, R0, C8, C7, 0& nbsp @ Invalidate tlbs MCR P15, 0, R0, C7, C5, 0 @ invalidate icache MCR P15, 0 , R0, C7, C5, 6 @ Invalidate BP array mcr p15, 0, R0, C7, C10, 4 & nbsp;@ DSB mcr p15, 0, R0, C7, C5, 4 @ ISB//close mmu cache &NBSP ; MRC P15, 0, R0, C1, C0, 0 BIC r0, R0, #0x00002000 @ clear bits (--v-) BIC r0, R0, #0x00000007 @ Clear bits 2:0 (-cam) Orr R0, R0, #0x00000002 &nbs p;@ Set bit 1 (--a-) Align Orr R0, R0, #0x00000800 @ set bit one (Z---) BTB #ifdef CONFIG_SYS_ICAC He_off BIC r0, R0, #0x00001000 @ Clear Bit (I) I-cache #else Orr R0, R0, #0x0000 1000 @ set Bit (I) i-cache #endif MCR P15, 0, R0, C1, C0, 0//Call initialization functions MOV IP, lr @ persevere link reg across call
