ARM Cortex Design Considerations for Debug

JTAG is the traditional mechanism for debug connections for ARM7/9 parts, but with the Cortex-m family, ARM introduced th E Serial wire Debug (SWD) Interface. SWD is designed-to-reduce the pin count required for debug from the 5 used by JTAG (including GND) to 3. In addition, one of the pins freed to this can is used for the low cost SWO tracing technology-for more details see T He FAQ "Overview of Trace support in Lpcxpresso IDE".

The SWD/SWV pins is overlaid on top of the JTAG pins as follows:

Some MCUs do not include internal pull-up or pull-down resistors on jtag/swd pins. You'll need to review the datasheet for the specific MCU being used to confirm. Where internal resistors is not provided, these should be added externally onto your board as detailed above. Resistors between 10K and 100K for these signals. This would prevent the signals from floating when they is not connected to anything. Failure to does this would leads to, at best, unreliable debug connections, or more likely no ability to debug at all.

The If an internal resistor are provided for a pin by the MCU and then an external resistor are not required for that pin. But if external resistor was provided in such cases, then it must match this provided internally by the MCU.

Note for TCK/SWCLK, although a pull-down are recommended, you can alternatively use a pull-up. The main thing is this it does not float. Note in particular so if the MCU provides an internal pull-up on this signal and then adding a external pull-down on the B Oard is not recommended.

Note that cortex-m0/m0+ parts does not the support SWV trace.

Other important debug related signals

When designing your board, you should also take the following signals to account for debug purposes. Failure to does this would leads to, at best, unreliable debug connections, or more likely no ability to debug at all.

• RESET
• Connect this pin to the (active low) reset input of the target MCU
• We would strongly recommend also including RESET in addition to Swdio, CLK and GND. For debugging, the tools-May-try-to-pull certain circumstances (depending upon debug probe, Debug Configuration SE Ttings and tools).
• Isp
• Most NXP MCU's has an ISP pin which (when pulled low) can is used to cause the MCU into enter a bootloader on reset.
• For example on Lpc17xx the is P2.10 and on lpc11xx and lpc13xx it is P0.1.
• Always ensure so you had a 10K to 100K Ohm pulling up resistor on the ISP pin, otherwise is unlikely to being able to ma Ke a successful debug connection.
• Vtref
• The Voltage target Reference pin supplies Some debug probes (such as LPC-LINK2) with the debug rail Voltage of the target To match its I/O logic level. For more information, see "Logic Levels and Ground" below.
• RTCK, Dbgsel
• Some NXP LPC2000 Devices has special pins that enable the JTAG interface. For example, on the NXP LPC2129 the signal RTCK must is driven low during RESET to enable the JTAG interface. Want to add jumpers to your hardware to accomplish this.

Logic Levels and Ground

Vtref (the Voltage target Reference pin, direction from target to debug probe) supplies Some debug probes such as Lpc-link  2 and Red probe+ with the debug rail voltage of the target to match its I/O logic level.  Vtref can tied directly to the target Vddio rail or through a resistor. If Vtref is tied high through a resistor, its value must be no greater than 100Ω.

The original LPC-LINK1 only supported 3.3V and does not require vtref whereas the LPC-LINK2 uses dual-supply buffers that a Llows the LINK2 to work with targets using a different voltage (between 1.8v-4.3v).

On the LPC-LINK2, when JP2 was shunted this would power the target side of the dual-supply buffer and provide power to the T  Arget through a diode on vtref. With JP2 open the target must supply the VTREF to power the target side of the dual-supply buffer.

When a debug probe attempts to adjust logic levels based on the voltage it sees on vtref, this is referenced to whatever G ND it has to work with. The voltage at Vtref are coming from your target and thus you need a good GND and shared with your target hardware.

Note that debug probes can is killed (like most USB devices) by excessive through current through ground of the probe and BAC K through the PC used for debugging. The usual cause of the your target has it's own PSU and have a ground differential slightly different from your de Bug PC. Please don't rely on your debug probe to ground your PC to the same potential as your target.

Power

Even when you had designed your debug circuit according to the above considerations, you should also check that Sufficien T power is being supplied to your target with order to obtain a reliable debug connection. If you were using a USB port on your PC to power your target, make sure that your PC was able to supply the required power O Ver usb-many PC USB ports do not meet USB power requirements.

Debug Connector pinouts

ARM have defined three debug connector pinouts that is in common use, a "traditional" pin connector, a Cortex ten pin co Nnector and a Cortex pin DEBUG+ETM connector ...

• This connector were originally defined for connection to ARM7/9 parts over JTAG, but are still sometimes found in cortex-m s Ystems (for connections over JTAG or SWD).
• Note that RTCK (Return clock) are only used on older ARM cores (ARM7TDMI and ARM9 family) before the debug was properly Dec Oupled from the core clock domain.
• Dimensions of the ARM JTAG connector is 1.29 "x 0.722" (33mm x 18.5mm).

• Suitable connector headers include:
• harwin:m50-3500542
• mouser:855-m50-3500542
• Samtec shrouded Header:ftsh-105-01-f-d-k
• The 10-pin Samtec ftsh-105-01 Connector has the dimensions:0.25 "x 0.188" (6.35mm x 4.78mm).
• Some boards use un-shrouded 10-pin headers. Always ensure this you connect your cable correctly, typically by matching the "1" marked on the board to the Red-stripe On the cable.
• The 10-pin cable is Samtec part number Ffsd-05-d-12.00.01-n

• This small 20-pin (0.05 ") connector provides access to SWD, SWV, JTAG, and ETM (4-bit) signals available on CORTEX-M3/M4 D Evices.
• The 20-pin header (Samtec ftsh-110-01) has the dimensions:0.50 "x 0.188" (12.70mm x 4.78mm).
• Although Lpcxpresso IDE does not currently support the direct use of the ETM (Embedded Trace macrocell), a number of board s use this form of connector as one of or as their main debug connector.
• A Special Cortex 10-pin Debug, Cortex 20-pin Debug+etm connector cable would typically be required to debug such board S.

ARM Cortex Design Considerations for Debug