ARM processor Architecture "Go"

ARM Processor Architecture

Transferred from: http://www.arm.com/zh/products/processors/instruction-set-architectures/index.php

The ARM architecture is the foundation for building each arm processor. The ARM architecture continues to evolve over time, and includes architectural capabilities to meet growing new capabilities, high-performance requirements, and emerging market needs. For information on the most recent release, see ARMV8 Architecture。

The ARM architecture supports implementations spanning multiple performance points, and has become the dominant architecture in many market segments. The ARM architecture supports a very wide range of performance points, enabling minimal ARM processor implementations and highly effective advanced design implementations with the latest micro-architecture technology. Achieving scale, performance, and low power consumption are key features of the ARM architecture.

ARM has developed architecture extensions to support Java Acceleration (jazelle®), Security (trustzone®), SIMD, and Advanced SIMD (NEON™) technologies. The ARMV8-A architecture adds password extensions as an optional feature.

The ARM architecture is similar to the thin instruction set computing (RISC) architecture because it contains the following typical RISC architecture features:

• The Unified register file load/store schema, where data processing operations are only for register content and not directly for memory content.
• Simple addressing mode, where all load/store addresses are determined only by register contents and instruction fields.

Enhancements to the basic RISC architecture enable ARM processors to achieve high performance, smaller code sizes, lower power consumption, and a good balance of smaller silicon areas.

• A64

• A32 (ARM)

• T32 (THUMB)

• Resources

ARM (commonly referred to as A32) is a fixed-length (32-bit) instruction set. It is the underlying 32-bit ISA used in the ARMV4T, Armv5tej, and ARMV6 architectures. In these architectures, the instruction set is used for applications that require high performance, or for handling hardware exceptions such as interrupts and processor startup.

For performance-critical applications and legacy code, the Cortex™-a and cortex-r profiles of the Cortex architecture also support ARM ISA. Most of its features are included in the Thumb instruction set introduced with Thumb-2 technology. Thumb (T32) benefits from improved code density.

The ARM instruction is 32 bits long and requires 4-byte boundary alignment.

Most ARM directives can be "conditioned" so that they are executed only when a specific condition code is set by the previous instruction. This means that if the N, Z, C, and V flags in the application State register meet the conditions specified in the directive, the instruction will only play its normal role in the programmer's model operations, memory, and coprocessor. If these tokens do not meet this condition, the instruction is used as a NOP, that is, the execution of the procedure normally goes to the next instruction (including any related checks on the exception), but does not play any other role. This conditional directive allows a small portion of the IF and while statements to be encoded without using a jump instruction.

The condition code includes:

Condition Code	meaning
N	The negative condition code, if the result is negative, is set to 1
Z	0-piece code, set to 1 if the result of the instruction is 0
C	A carry condition code that is set to 1 if the instruction generates a rounding condition
V	The overflow condition code, set to 1 if the directive generates an overflow condition.

ARM processor Architecture "Go"