Arm start and interrupt vector table

Startup Method

For S3C2440, there are two boot Methods: nor flash and NAND Flash.

Start with nor flash

The address range of nor flash is as follows:

0x0000. -0x0800.0000 (2 m nor flash)

The bootsram address in the chip is set

0x4000. 109-0x4000.dfff (4 K bootsram)

Because the code can be directly run in nor flash, bootsram is mapped to another address for other purposes.

Program images are directly stored in nor flash, and the interrupt vector table is stored in a space of 8 × 4 starting from 0x0000. 0000.

When an interruption occurs, the PC is set to the corresponding vector address. For example, when you power on or press the reset key, the PC is directly set to 0x00, starting from 0x00 of nor flash.

Start with NAND Flash

In this case, the bootsram address in the chip is set

0x0000. 109-0x0800.0000 (4 K bootsram)

Connecting the NAND flash Address to nfce

Since Code cannot be run in NAND Flash, it must be copied to the memory before running.

Program images are stored in NAND Flash, and the interrupted vector table is located at the beginning of the program image. Because NAND Flash cannot run code, when the system is powered on or reset, the built-in NAND Flash will use the access control interface, the interrupt vector table and Boot Code are automatically loaded into the internal SRAM (the SRAM is located at the starting address space of 0x00000000 and the capacity is 4 kb ), set the Pc value to 0x00 to run the program (all of which are completed by the hardware logic in the chip ). Then, the boot program in the SRAM loads the operating system image into the SDRAM, and the operating system can run in the SDRAM. After the startup is completed, the 4 kb startup SRAM can be used for other purposes.

Interrupt vector table settings

There are 7 types of exceptions and interruptions in arm.

 

From high to low by response priority	Order by interrupt vector table
Reset	Reset
Data abort	Undefined instruction interruption
FIQ	SWI
IRQ	Prefetch command abort
Prefetch command abort	Data abort exception
Undefined commands, SWI	IRQ
	FIQ

Arm requires that the interrupt vector table be placed in a space of 8 × 4 bytes in a row starting from 0 (arm720t and arm9and arm10 also support the High address vector table starting from 0xffff0000 ), the positions of the exception and interrupt vectors in the vector table are as follows:

 

Address	Interrupted
0x00	Reset
0x04	UNDEF
0x08	SWI
0x0c	Prefetch abort
0x10	Data abort
0x14	(Reserved)
0x18	IRQ
0x2c	FIQ

When an interrupt occurs, the ARM processor forces the PC pointer to be the vector address corresponding to the interrupt vector table. Because each interrupt vector has only one byte of storage space in the vector table and only one instruction can be stored, the jump instruction is usually stored so that the program jumps to another place in the memory and then executes the interrupt processing.

 

The Program for implementing the interrupt vector table is usually as follows: Area boot, code, readonly Entry B reset_handler; reset_handler is a label B undef_handler B swi_handler B preabort_handler B dataabort_handler B; for reserved interrupt, stop here B irq_handler B fiq_handler

The keyword entry specifies that the compiler retains this code, because the compiler may consider this code as redundant code and optimize it. Make sure that the code is connected to the zero address and serves as the entry point of the entire program. (The entry is not always used to set the entry point of the program, therefore, you usually need to explicitly set the program entry point in the Link options ).