Atom is intended to be "the smallest particle that cannot be further split", while atomic operation)

1. Introduction

Atom is intended to be "the smallest particle that cannot be further divided", and atomic operation is "one or more operations that cannot be interrupted ". It is a little complicated to implement atomic operations on a multi-processor. In this article, let's talk about how the Intel processor and Java implement atomic operations.

2. Definition of Terms

Terms	English	Explanation
Cache row	Cache line	Minimum operating unit of the cache
Compare and exchange	Compare and swap	For the CAS operation, you need to enter two values, one old value (the value before the expected operation) and one new value. During the operation, you must first compare whether the old value has changed. If not, to the new value.
CPU Assembly Line	CPU Pipeline	The CPU assembly line works like an assembly line in industrial production ~ Six circuit units with different functions form a command processing pipeline, and then divide an x86 command into 5 ~ After six steps, these circuit units will execute them separately, so that an instruction can be completed in a CPU clock cycle, thus improving the computing speed of the CPU.
Memory sequence conflict	Memory order violation	Memory sequence conflicts are generally caused by false sharing. False sharing means that multiple CPUs modify different parts of the same cache row at the same time, resulting in invalid operations on one CPU, when the memory sequence conflicts, the CPU must clear the pipeline.

3. How can a processor perform atomic operations?

The 32-bit IA-32 processor implements atomic operations between multiple processors by locking the cache or bus.

3.1 The processor automatically guarantees the atomicity of basic memory operations

First, the processor automatically guarantees the atomicity of basic memory operations. The processor ensures that one byte is read from or written to the system memory, which means that when one processor reads one byte, Other Processors cannot access the memory address of this byte. The Pentium 6 and the latest processors can automatically ensure that a single processor performs 16/32/64-bit operations on the same cache row, but the complex memory operation processor cannot automatically guarantee its atomicity, for example, cross-bus width, cross-Cache rows, and cross-page table access. However, the processor provides two mechanisms: Bus lock and cache lock to ensure the atomicity of complex memory operations.

3.2 use bus locks to ensure atomicity

The first mechanism is to ensure atomicity through bus locks. If multiple processors simultaneously perform read-write (I ++ is a classic read-write operation) operations on shared variables, the shared variables will be operated by multiple processors at the same time, in this way, the read rewrite operation is not Atomic. After the operation, the value of the shared variable is inconsistent with the expected one. For example, if I = 1, we perform the I ++ operation twice. The expected result is 3, but the possible result is 2. For example