Chapter 9 do what you want -- teach you what is truly an arbitrary division

I. Why do I want to say arbitrary frequency division?

Maybe the first experiment in FPGA should be a crossover experiment, rather than a flow lamp, or the "Hello World" display of lcd1602, because the concept of division is extremely important in FPGA. When we first arranged the flow light, we just wanted to let everyone see the effect and stimulate your interest (the same is true for MCU learning ).

In most textbooks, we will talk about how to divide the data, including odd, even, and decimal. Some textbooks will also talk about the principle of arbitrary division (half-division, any division). It uses a phase and circuit, and cannot achieve a 50% duty cycle, which is not very flexible.

However, none of the textbooks will talk about precise, easy-to-understand, high-precision arbitrary division principle (at least Bingo has never seen it), and there is no design that can use the same circuit to control any frequency. Bingo was inspired by the principle of the phase accumulators for any waveform generator in the past, and summed up the important thinking of high-precision arbitrary frequency synthesis. It has contributed to everyone and hoped to be useful to everyone.

Ii. principle and performance of arbitrary Frequency Division

1. Dds phase Accumulators

(1) DDS synthesis process

First, describe the principle of DSS (direct frequency synthesis.

DDS is an important method for frequency synthesis, and has an extremely important application in waveform generators. DDS consists of the following parts:

A) phase Accumulators

B) read Ram data

C) D/A converter

D) low-pass filter

See the following flowchart: the flowchart of direct frequency synthesis includes fixed modules, input frequency controllers, and output fixed frequency waveforms.

The main module of this circuit is the phase accumulators. The ram data is read cyclically through the phase accumulators to obtain waveform data at a fixed frequency.

(2) Principle of phase Accumulators

The process of phase accumulation is as follows:

Input frequency control word, accordingAlgorithmTo realize the phase change. The analysis is as follows:

Assume that the FPGA benchmark frequency is 50 MHz, that is, the benchmark frequency:

(MHz)

Assume that the counter is a 32-bit counter;

If K is the frequency control word, the phase output frequency is:

(1)

That is

(2)

Based on the phase accumulation principle and the data read by the RAM cache, the RAM data is read at an interval of K every cycle.

When k = 1, the formula can output the minimum frequency. according to formula (1 ):

Therefore, the minimum waveform frequency step is 0.011655Hz.

When fo = 1Hz, follow the formula (2)

Therefore, the step of K increase/decrease per Hz is 85.90.

When K = n/2, the formula can output the maximum frequency (because each CLK hop is changed once). At this time, according to formula (1), the following result is obtained:

Therefore, the waveforms with Fixed frequencies can be output according to the change of frequency control word K.

2. Principle of arbitrary Frequency Division

In some FPGA applications, when the frequency requirement is relatively high, the method of generating a fixed frequency using the principle of phase accumulators is unavoidable.

We stipulate that the CNT should be split in half 50% as follows:

(1) When, that is, low level;

(2) When, fo = 1, that is, high level.

Same as above:

Used in FPGACodeAs follows:

/*************************************** ************

* Module name: clk_generator

* Engineer: crazy bingo

* Target device: ep2c8q208c8

* Tool versions: Quartus II 9.1sp1

* Create Date: 2011-6-25

* Revision: V1.0

* Description:

**************************************** **********/

/*************************************** **********

Fc = 50 MHz 50*10 ^ 6

Fo = FC * k/(2 ^ 32)

K = fo * (2 ^ 32)/FC

= Fo * (2 ^ 32)/(50*10 ^ 6)

**************************************** **********/

Module clk_generator

#

(

Parameter freq_word = 32 'd8590 // 1 kHz

)

(

Input CLK, // 50 MHz

Input rst_n, // clock reset

Output Reg clk_out

);

//--------------------------------------

Reg [31: 0] max_value;

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

Max_value <= 1' B0;

Else

Max_value <= max_value + freq_word;

End

//--------------------------------------

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

Clk_out <= 1' B0;

Else

Begin

If (max_value <32 'effecfff _ FFFF)

Clk_out <= 1' B0;

Else

Clk_out <= 1 'b1;

End

End

Endmodule

This Code is based on the principle of arbitrary Frequency Division summarized by bingo from the DDS phase accumulators. This module is applied to multiple projects with high frequency accuracy requirements (such as UART, to obtain a BPS of Hz, we can use this principle to obtain a precise method, which can improve the accuracy of data transmission to a certain extent ).

The principle of arbitrary division of the phase accumulators in DDS can also be applied in general engineering. In some application scenarios, it is worth considering. This application is purely a subjective application of Bingo. If you have any objection, contact me.