Compilation Basics (3) Operations and logic directives

Operations and Logic directives

Most operations and logic directives affect the processor's status tag register.

As can be seen from the above figure, this is the status Mark Register is a 16-bit register

Each bit is called a flag bit and can be valued at 1 or 0. Carry flag Carry Flag (CF)-An unsigned (unsigned overflow) overflow occurs when the bit is set to 1. For example, calculate 255+1 (the result exceeds 0 ... 255). This bit is 0 when there is no overflow. 0 flag Zero Flag (ZF)-When the result is 0 set to 1, the result is not 0 when set to 0. Sign symbol sign Flag (SF)-the result is negative 1 and the result is positive for 0. In fact, this bit is particularly important for results. Overflow flag Overflow Flag (of)-when a signed number overflow appears set to 1. For example, calculate 100+50 (the result exceeds the range of-128-127). Parity flag Parity Flag (PF)-When the number of 1 in the result operand is even 1, otherwise 0 note that if the result is a word, the flag indicates only the low 8 bits. Auxiliary carry flag Auxiliary flag (AF)-Low 4-bit upward carry 1, otherwise 0 (the value of the 3rd bit (half byte) generated when the operation is recorded. For example, when executing the addition instruction, the most significant bit has a carry time of 1, otherwise 0 interrupt flag Interrupt Enable flag (IF)-when the CPU is allowed to interrupt is 1, otherwise 0 Direction flag (DF)-direction flag, in the string processing instructions to control the direction of processing information Use. When DF is 1 o'clock, the variable address registers Si and Di decrement after each operation, so that the string processing is processed from the high address to the low address direction. When DF is 0 o'clock, the SI and di increments are made so that the string processing is processed from the low address to the high address direction.

Here are 3 sets of instructions.

First group: ADD, SUB,CMP, and, TEST, OR, XOR

The following operands are supported:

REG, Memory

Memory, REG

Reg, Reg

Memory, Immediate

REG, Immediate

REG (Register): AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.

Memory (RAM): [BX], [bx+si+7], variable, etc...

Immediate (immediate number): 5, -24, 3Fh, 10001101b, etc...

Once executed, the results are often stored in the first operand. The CMP and test directives only affect the flag bit and do not return a numeric value (the two instructions are used to determine the program's operation) the above directive affects only the following flags:

CF, ZF, SF, OF, PF, AF. Add-Adds a second operand to the first operand SUB-subtracts the second operand from the first operand CMP-subtracts the second operand from the first operand, but only affects the flag bit. And-two operands each bit of logic and operation. The algorithm is as follows
1 and 1 = 1
1 and 0 = 0
0 and 1 = 0
0 and 0 = 0
Only if two operands are 1 o'clock, the result of the operation is 1. TEST-the same as the above and operation, but only affects the flag bit. Or-two operands each bit logical OR operation. The algorithm is as follows
1 OR 1 = 1
1 OR 0 = 1
0 OR 1 = 1
0 OR 0 = 0
If there are 1 in the operand then the result must be 1. XOR-The logical XOR operation of each bit of the two operands. The algorithm is as follows
1 XOR 1 = 0
1 XOR 0 = 1
0 XOR 1 = 1
0 XOR 0 = 0
When the two operands are not the same, the result is 1.

Group II: MUL, Imul, DIV, Idiv

The following operands are supported:

Reg

Memory

REG (Register): AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.

Memory: [BX], [bx+si+7], variable, etc ...

The MUL and Imul directives only affect the CF, the mark bit.

If the result is out of range after the operation, these marker positions are 1, if no more than

Range, set 0

DIV and Idiv directives have no effect on the flag bit MUL-unsigned multiplication:
When the operand is a byte:
AX = AL * operand.
When the operand is a word:
(DX ax) = ax * operand. Imul-Signed multiplication:
When the operand is a byte:
AX = AL * operand.
When the operand is a word:
(DX ax) = ax * operand. DIV-Unsigned Division:
When the operand is a byte:
AL = AX/operand
AH = remainder (the remainder after modulo).
When the operand is a word:
Ax = (DX ax)/operand
DX = remainder (the remainder after modulo) Idiv-Signed Division:
When the operand is a byte:
AL = AX/operand
AH = remainder (the remainder after modulo)
When the operand is a word:
Ax = (DX ax)/operand
DX = remainder (the remainder after modulo).

Group III: INC, DEC, not, NEG

The following operands are supported:

Reg

Memory

REG (Register): AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.

Memory: [BX], [bx+si+7], variable, etc ...

INC, the DEC directive only affects the following flag bits:

ZF, SF, OF, PF, AF.

The not directive does not affect any flag bits.

The NEG I directive affects only the following operation bits:

CF, ZF, SF, OF, PF, AF. Not-pair with operand each bit counter NEG-the operand is reversed

In fact it is reversed on each bit and then in the last one plus 1. For example 5 will become -5,-2 will become 2. (The operation in this case should be a complement operation within the computer)