Complete nginx source code annotation (5) Core/ngx_cpuinfo.c

/** Copyright (c) Igor Sysoev * copyright (c) nginx, Inc. */# include <ngx_config.h> # include <ngx_core.h> // If the CPU architecture is i386 or amd64 and the compiler is GNU Compiler or Intel compiler, define the cngx_puid function // otherwise, the ngx_cpuid function is empty # If (_ i386 _ | _ amd64 __) & (_ gnuc _ | _ intel_compiler) Static ngx_inline void ngx_cpuid (uint32_t I, uint32_t * BUF); // The CPU in the i386 architecture calls the CPU command cpuid, obtain CPU information # If (_ i386 _) Static ngx_inline voidngx_cpuid (uint32_t I, uint32_t * BUF) {/** we cocould not use % EBX as output parameter if GCC builds pic, * and we cocould not save % EBX on Stack, because % ESP is used, * When the-fomit-frame-pointer optimization is specified. */_ ASM _ ("mov % EBX, % ESI;" "cpuid;" "mov % eax, (% 1 ); "" mov % EBX, 4 (% 1); "mov % edX, 8 (% 1);" "mov % ECx, 12 (% 1 ); "" mov % ESI, % EBX; ":" A "(I)," D "(BUF):" ECx "," edX "," ESI ", "Memory");} // CPU in the amd64 architecture. Call the CPU command cpuid to obtain CPU information # else/* _ amd64 _ */static ngx_inline voidngx_cpuid (uint32_t I, uint32_t * BUF) {uint32_t eax, EBX, ECx, EDX; // inline assembly. For more information, see my previous two blog posts // GCC inline assembly (1) get started // GCC inline assembly (2) simple example of GCC generation assembly code _ ASM _ ("cpuid": "= A" (eax ), "= B" (EBX), "= C" (ECx), "= D" (EDX): "A" (I )); // The return value is assigned to the Buf in four General registers, and the Buf [0] = eax; Buf [1] = EBX; Buf [2] = edX in external calls; buf [3] = ECx;} # endif/* Auto Detect the L2 cache line size of modern and widespread CPUs */voidngx_cpuinfo (void) {// string recognized by the storage vendor, that is, vendor ID u_char * vendor; // vbuf is used as the buffer for the data obtained when eax = 0 // CPU description obtained when eax = 1 // The model is calculated based on the extended model and model in the CPU description. value of uint32_t vbuf [5], CPU [4], model; vbuf [0] = 0; vbuf [1] = 0; vbuf [2] = 0; vbuf [3] = 0; vbuf [4] = 0; // function of cpuid 0th (eax = 0 ), obtain the maximum function number and vendor identification string // vbuf [0] maximum storage function number // vbuf [1], vbuf [2], vbuf [3] storage vendor Identification No. ngx_cpuid (0, vbuf); vendor = (u_char *) & vbuf [1]; If (vbuf [0] = 0) {return ;} // cpuid 1st (eax = 1 ), obtain CPU instructions //-Stepping //-model //-family //-Processor type //-extended model // 27:20-extended family ngx_cpuid (1, CPU); // if the vendor ID is Intel's if (ngx_strcmp (vendor, "genuineintel") = 0) {// switch (CPU [0] & 0xf00)> 8) {/* Pentium */case 5: ngx_cacheline_size = 32; Break Based on the Intel CPU family number; /* Pentium Pro, II, III */case 6: // The value of cacheline is 32 ngx_cacheline_size = 32; // according to extended model and model, to determine the cacheline in this case. For example, if the extended model is 0x1 and the model is 0xd, the value of the model variable is 0x1d0, which is greater than 0xd0, if // For example, if the extended model is 0x0 and the model is 0xd, the value of the model variable is 0x0d0, which is equal to 0xd0. If // For example, the extended model is 0x0, if the model is 0xc, the value of the model variable is 0x0c0, which is less than 0xd0. If model = (CPU [0] & 0xf0000)> 8) | (CPU [0] & 0xf0); If (Model> = 0xd0) {/* Intel Core, Core 2, Atom */ngx_cacheline_size = 64;} break; /** Pentium 4, although its cache line size is 64 bytes, * It prefetches up to two cache lines during memory read * // The cacheline is also 64-bit, however, when reading the data in the memory prefetch, the length of the cacheline will be twice. Case 15: ngx_cacheline_size = 128; break;} // if the vendor ID is amd} else if (ngx_strcmp (vendor, "authenticamd") = 0) {ngx_cacheline_size = 64 ;}# elsevoidngx_cpuinfo (void) {}# endif

Reference

1. Cpuid-Wikipedia

Complete nginx source code annotation (5) Core/ngx_cpuinfo.c